CY28354-400 Datasheet, PDF (1/8 Pages) SpectraLinear Inc – 210 MHz 24 Output Buffer for 4-DDR DIMMS for VIA Chipsets Support

CY28354-400
210 MHz 24 Output Buffer for 4-DDR DIMMS for VIA Chipsets
Support
Features
Functional Description
• Supports VIA PRO 266, KT266 and P4x266
• Dual 1- to 12-output buffer/driver
• Supports up to four DDR DIMMs
• Low-skew outputs (< 75 ps)
• Supports 266-MHz, 333-MHz and 400-MHz DDR SDRAM
• SMBus Read and Write support
• Space-saving 48-pin SSOP package
The CY28354-400 is a 2.5V buffer designed to distribute
high-speed clocks in PC applications. The part has 24 outputs
to support four unbuffered DDR DIMMS. The CY28354-400
can be used in conjunction with CY28326 similar clock synthe-
sizer for the PTT880 and KTT880 chipsets.
The CY28354-400 also includes an SMBus interface which
can enable or disable each output clock. On power-up, all
output clocks are enabled.
Block Diagram
BUF_INA
ADDR_SEL
SDATA
SCLOCK
I2C_CS
SMBus
Decoding
BUFF_INB
FB_OUTA
DDRAT0
DDRAC0
DDRAT1
DDRAC1
DDRAT2
DDRAC2
DDRAT3
DDRAC3
DDRAT4
DDRAC4
DDRAT5
DDRAC5
DDRBT0
DDRBC0
DDRBT1
DDRBC1
DDRBT2
DDRBC2
DDRBT3
DDRBC3
DDRBT4
DDRBC4
DDRBT5
DDRBC5
FB_OUTB
Pin Configuration
VDD2.5
GND
FB_OUTB
BUFF_INB
DDRBT0
DDRBC0
DDRBT1
DDRBC1
GND
VDD2.5
DDRAT0
DDRAC0
DDRAT1
DDRAC1
GND
VDD2.5
FB_OUTA
BUF_INA
DDRAT2
DDRAC2
DDRAT3
DDRAC3
VDD2.5
GND
SSOP
Top View
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
VDD2.5
GND
ADDR_SEL
I2C_CS
DDRBT2
DDRBC2
DDRBT3
DDRBC3
GND
VDD2.5
DDRAT4
DDRAC4
DDRAT5
DDRAC5
GND
VDD2.5
DDRBT4
DDRBC4
DDRBT5
DDRBC5
VDD2.5
GND
SDATA
SCLK
Rev 1.0, November 22, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:[phone] Fax:[phone]
Page 1 of 8
www.SpectraLinear.com