CY28351 Datasheet, PDF (1/7 Pages) Cypress Semiconductor – Differential Clock Buffer/Driver DDR400- and DDR333-Compliant

CY28351
Differential Clock Buffer/Driver
Features
• Supports 333-MHz and 400-MHz DDR SDRAM
• 60- – 200-MHz operating frequency
• Phase-locked loop (PLL) clock distribution for double
data rate synchronous DRAM applications
• Distributes one clock input to ten differential outputs
• External feedback pin (FBIN) is used to synchronize the
outputs to the clock input
• Conforms to the DDRI specification
• Spread Aware for electromagnetic interference (EMI)
reduction
• 48-pin SSOP package
Description
This PLL clock buffer is designed for 2.5-V_DD and 2.5-AV_DD
operation and differential outputs levels.
This device is a zero delay buffer that distributes a clock input
(CLKIN) to ten differential pairs of clock outputs (YT[0:9],
YC[0:9]) and one feedback clock output (FBOUT). The clock
outputs are individually controlled by the serial inputs SCLK
and SDATA.
The two-line serial bus can set each output clock pair (YT[0:9],
YC[0:9]) to the Hi-Z state. When AV_DD is grounded, the PLL is
turned off and bypassed for the test purposes.
The PLL in this device uses the input clock (CLKIN) and the
feedback clock (FBIN) to provide high-performance, low-skew,
low-jitter output differential clocks.
Block Diagram
SCLK
SDATA
CLKIN
FBIN
AVDD
Serial
Interface
Logic
PLL
10
YT0
YC0
YT1
YC1
YT2
YC2
YT3
YC3
YT4
YC4
YT5
YC5
YT6
YC6
YT7
YC7
YT8
YC8
YT9
YC9
FBOUT
Pin Configuration
VSS 1
YC0 2
YT0 3
VDDQ 4
YT1 5
YC1 6
VSS 7
VSS 8
YC2 9
YT2 10
VDD
11
SCLK 12
CLKIN 13
NC 14
VDDI 15
AVDD 16
AVSS 17
VSS 18
YC3 19
YT3 20
VDDQ 21
YT4 22
YC4 23
VSS 24
48 VSS
47 YC5
46 YT5
45 VDDQ
44 YT6
43 YC6
42 VSS
41 VSS
40 YC7
39 YT7
38 VDDQ
37 SDATA
36 NC
35 FBIN
34 VDDQ
33 FBOUT
32 ^NC
31 VSS
30 YC8
29 YT8
28 VDDQ
27 YT9
26 YC9
25 VSS
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
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