CY28326 Datasheet, PDF (1/22 Pages) Cypress Semiconductor – FTG for VIA PT880 Serial Chipset

CY28326
FTG for VIA PT880 Serial Chipset
Features
• Supports P4^£ CPUs
• 3.3V power supply
• Ten copies of PCI clocks
• One 48 MHz USB clock
• Two copies of 25 MHz for SRC/LAN clocks
• One 48 MHz/24 MHz programmable SIO clock
Block Diagram
• Three differential CPU clock pairs
• SMBus support with Byte Write/Block Read/Write
capabilities
• Spread Spectrum EMI reduction
• Dial-A-Frequency^® features
• Auto Ratio features
• 48-pin SSOP package
Pin Configuration^[1]
XIN
XOUT
PLL1
CPU_STP#
IREF
FS[A:D]
Power
on
Latch
VTTPWRGD#
/2
PCI_STP#
MODE
PLL2
PD#
SDATA
SCLK
WD
Logic
I2C
Logic
REF[0:2]
CPUT[0:2]
CPUC[0:2]
25MHz[0:1]
AGP[0:2]
PCI[0:6]
PCI_F[0:2]
48MHz
24_48MHz
SRESET
**FSA/REF0 1
48
**FSB/REF1 2
47
VDDREF 3
46
XIN 4
45
XOUT 5
44
VSSREF 6
43
*FSC/PCIF0 ₇
42
*FSD/PCIF1 8
41
*Mode/PCIF2 9
40
VDDPCI 10
39
VSSPCI 11
38
PCI0 12
37
PCI1 ¹³
36
PCI2 ¹⁴
35
PCI3 15
34
PCI4 16
33
VDDPCI 17
32
VSSPCI 18
31
*(PCI_STP#)/Ratio0/PCI5 19
30
*(CPU_STP#)/Ratio1/PCI6 20
29
48MHz 21
28
**24_48_SEL/24_48MHz 22
27
VSS48 23
26
VDD48 24
25
48 Pin SSOP
VDDA
VSSA
IREF
CPUT2
CPUC2
VSSCPU
CPUT1
CPUC1
VDDCPU
CPUT0
CPUC0
VSSSRC
25MHz1
25MHz0
VDDSRC
*VTT_PWRGD/*PD#
SDATA
SCLK
SRESET#
AGP2
VSSAGP
VDDAGP
AGP1/*RatioSel
AGP0
Note:
1. Pins marked with [*] have internal 150k:pull-up resistors. Pins marked with [**] have internal 150k:pull-down resistors.
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:[phone] Fax:[phone]
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