CY2280 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 100-MHz Pentium II Clock Synthesizer/Driver with Spread Spectrum for Mobile or Desktop PCs

Y2280
CY2280
100 MHz Pentium^® II Clock Synthesizer/Driver with Spread
Spectrum for Mobile or Desktop PCs
Features
Functional Description
• Mixed 2.5V and 3.3V operation
• Clock solution for Pentium® II, and other similar
processor-based motherboards
— Four 2.5V CPU clocks up to 100 MHz
— Eight 3.3V sync. PCI clocks, one free-running
— Two 3.3V 48-MHz USB clocks
— Three 3.3V Ref. clocks at 14.318 MHz
— Two 2.5V APIC clocks at 14.318 MHz or PCI/2
• EMI control
— Spread spectrum clocking
— Factory-EPROM programmable spread spectrum
margin
— Factory-EPROM programmable output drive and
slew rate
• Factory-EPROM programmable CPU clock frequencies
for custom configurations
• Available in space-saving 48-pin SSOP package
The CY2280 is a Spread Spectrum clock synthesizer/driver for
a Pentium II, or other similar processor-based PC requiring
100-MHz support. All of the required system clocks are
provided in a space-saving 48-pin SSOP package. The
CY2280 can be used with the CY231x for a total solution for
systems with SDRAM.
The CY2280 provides the option of spread spectrum clocking
on the CPU and PCI clocks for reduced EMI. A downspread
percentage is introduced when the SEL_SS input is asserted.
The device can be run without spread spectrum when the
SEL_SS input is deasserted. The percentage of spreading is
EPROM-programmable to optimize EMI-reduction.
The CY2280 has power-down, CPU stop, and PCI stop pins
for power management control. The signals are synchronized
on-chip, and ensure glitch-free transitions on the outputs.
When the CPU_STOP input is asserted, the CPU clock
outputs are driven LOW. When the PCI_STOP input is
asserted, the PCI clock outputs (except the free-running PCI
clock) are driven LOW. When the PWR_DWN pin is asserted,
the reference oscillator and PLLs are shut down, and all
outputs are driven LOW.
Table 1. CY2280 Selector Guide.
CY2280 Configuration Options
Clock Outputs
–1
–11S
–21S
CPU (66.6, 100 MHz)
4
4
4
PCI (CPU/2, CPU/3)
8
8
8
USB (48 MHz)
2
2
2
APIC (14.318 MHz)
2
2
—
APIC (PCI/2)
—
—
2
Reference (14.318 MHz)
3
3
3
CPU-PCI delay
CPU-APIC delay
1.54.0 ns
—
1.54.0 ns
—
1.54.0 ns
2.0–4.5 ns
Spread Spectrum (Downspread)
N/A
0.6%
0.6%
Logic Block Diagram
CPU_STOP
XTALIN
XTALOUT
PWR_DWN
SEL0
SEL1
SEL100
SEL_SS
PCI_STOP
14.318
MHz
OSC.
CPU
PLL
Divider
EPROM
Delay
SYS PLL
-1
-2
STOP
LOGIC
STOP
LOGIC
APIC [0:1]
V_DDAPIC
REF [0-2]
V_DDREF
CPUCLK [0-3]
V_DDCPU
PCICLK_F
V_DDPCI
PCI [1-7]
V_DDPCI
USBCLK [0:1]
V_DDUSB
Rev 1.0, November 25, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:[phone] Fax:[phone]
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