CY2254A Datasheet, PDF (1/7 Pages) Cypress Semiconductor – Pentium Processor Compatible Clock Synthesizer/Driver

Y2254A
CY2254A
Pentium^® Processor Compatible Clock Synthesizer/Driver
Features
• Multiple clock outputs to meet requirements of most
Pentium^® motherboards
— Four pin-selectable CPU clocks @ 66.66 MHz, 60.0
MHz, and 50.0 MHz for support of Intel Triton^™ PCIset
based PC
— 55.0 MHz pin-selectable CPU clock also available (2
option only)
— Six PCI clocks at 1/2 CPU Clock frequency
— One I/O clock @ 24 MHz
— One Keyboard Controller clock @ 12 MHz (1 option)
or one Universal Serial Bus clock @ 48 MHz
(2 option)
— Two Ref. clocks @ 14.318 MHz
— Ref. 14.318 MHz Xtal oscillator input
• CPU clock jitter < 200 ps cycle-to-cycle
• Low skew outputs
— < 250 ps between CPU clocks
— < 250 ps between PCI clocks
— < 500 ps between CPU and PCI clocks (2 option)
— CPU clock leads PCI clock by +1 ns min. to +4 ns
max. (1 option)
Logic Block Diagram
XTALIN
XTALOUT
14.318
MHz
OSC.
S0
S1
SYS
PLL
y2
y2
CPU
PLL
ROM
y2
1 option only DELAY
OE
• Freq. stability = 0.01% (max.)
• Output duty cycle 45% min. to 55% max.
• Test mode support (1 option only)
• 3.3V or 5.0V operation
• Internal pull-up resistors on S0, S1, and OE inputs
Functional Description
The CY2254A is a Clock Synthesizer/Driver that provides the
multiple clocks required for a Pentium-based PC. The
CY2254A has low-skew outputs (< 250 ps between the CPU
Clocks, < 250 ps between the PCI Clocks). In addition, the
CY2254A CPU clock outputs have less than 200 ps
cycle-to-cycle jitter. Finally, both the PCI and CPU clock
outputs meet the 1 V/ns slew rate requirement of a Pentium
processor-based system.
The CY2254A accepts a 14.318 MHz reference signal as its
input. The CY2254A has 2 PLLs, one of which generates the
CPU and PCI clocks, and the other generates the I/O and
Keyboard Controller or USB clocks. The CY2254A runs off
either a 3.3V or 5V supply.
The CY2254A is available in two options. The 1 option
supports the Intel Triton PCIset and provides a 12 MHz
keyboard clock on pin 25. The 2 option provides a 48 MHz
USB clock on pin 25 and supports the Cyrix^® M1 processor.
REF0 (14.318 MHz)
REF1 (14.318 MHz)
KBDCLK (12 MHz)
IOCLK (24 MHz)
USBCLK (48 MHz)
CPUCLK0
CPUCLK1
CPUCLK2
CPUCLK3
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
Pin Configuration
Top View
SOIC
V_DD 1
XTALIN 2
XTALOUT 3
V_SS 4
OE 5
CPUCLK0 6
CPUCLK1 7
V_DD 8
CPUCLK2 9
CPUCLK3 10
V_SS 11
S1 12
S0 13
V_DD 14
28 REF0
27 REF1
26 VDD
25 SEEBELOW
24 IOCLK
23 VSS
22 PCICLK2
21 PCICLK3
20 VDD
19 PCICLK4
18 PCICLK5
17 VSS
16 PCICLK1
15 PCICLK0
OPTION
1
2
PIN 25
KBDCLK
12 MHz
USBCLK
48 MHz
Rev 1.0, November 25, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:[phone] Fax:[phone]
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