CY2210 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 133-MHz Spread Spectrum Clock Synthesizer/Driver with AGP, USB, and DRCG Support

Y2210
CY2210
133 MHz Spread Spectrum Clock Synthesizer/Driver
with AGP, USB, and DRCG Support
Features
Benefits
• Mixed 2.5V and 3.3V Operation
Usable with Pentium^® II and Pentium^® III processors
• Compliant to Intel^® CK133 (CY2210-3) & CK133W
(CY2210-2) synthesizer and driver specification
• Multiple output clocks at different frequencies
Single-chip main motherboard clock generator
— Four CPU clocks, up to 133 MHz
— Driven together, support 4 CPUs and a chipset
— Eight synchronous PCI clocks, 1 free-running
— Support for 4 PCI slots and chipset
— Two CPU/2 clocks, at one-half the CPU frequency
— Four AGP clocks at 66 MHz
— Three synchronous APIC clocks, at 16.67 MHz
— One USB clock at 48 MHz
— Two reference clocks at 14.318 MHz
— Drives up to two main memory clock generators, including
DRCG (CPUCLK/2)
— Support for multiple AGP slots
— Support multiprocessing systems
— Supports USB frequencies and I/O chip
• Spread Spectrum clocking
Enables reduction of EMI in some systems
— 32.5-kHz modulation frequency @ 133 MHz
— 33.1-kHz modulation frequency @ 100 MHz for
CY2210-02/03
— 33.4-kHz modulation frequency @ 100 MHz for
CY2210-04
— EPROM programmable percentage of spreading. Default
is –0.6%, which is recommended by Intel
• Power-down features
Supports mobile systems
• Three Select inputs
Supports up to eight CPU clock frequencies
• Low-skew and low-jitter outputs
Meets tight system timing requirements at high frequency
• OE and Test Mode support
Enables ATE and “bed of nails” testing
• 56-pin SSOP package
Widely available, standard package enables lower cost
Logic Block Diagram
CPU_STOP
XTALIN
XTALOUT
14.318
MHz
OSC.
SEL1
SEL0
SEL133
SPREAD
PCI_STOP
PWR_DWN
CPU
PLL
EPROM
SYS
PLL
Divider,
EPRO
M-
REFCLK [0–1] (14.318 MHz)
CPUCLK [0–3]
CPUCLK/2 [0–1] (DRCG)
PCICLK_F (33.33 MHz)
PCICLK [1–7] (33.33 MHz)
APICCLK [0–2] (16.67 MHz)
AGPCLK [0–3] (66.67 MHz)
USBCLK (48 MHz)
Pin Configuration
Top View
V_SSREF
1
REFCLK0 2
REFCLK1 3
V_DDREF
4
XTALIN 5
XTALOUT 6
V_SSPCI
7
PCICLK_F ₈
PCICLK1 ₉
V_DDPCI
10
PCICLK2 ₁₁
PCICLK3 ₁₂
V_SSPCI
13
PCICLK4 14
PCICLK5 ¹⁵
V_DDPCI
16
PCICLK6 ¹⁷
PCICLK7 18
V_SSPCI
19
V_SSAGP
20
AGPCLK0 ₂₁
AGPCLK1 22
V_DDAGP
23
V_SSAGP
24
AGPCLK2 25
AGPCLK3 ₂₆
V_DDAGP
27
SEL133 ₂₈
56
V_DDAPIC
55 ^APICCLK2
54 APICCLK1
53 APICCLK0
52
V_SSAPIC
51
V_DDCPU/2
50 CPUCLK/2
(DRCG)
49 CPUCLK/2
(DRCG)
48
V_SSCPU/2
47
V_DDCPU
46 CPUCLK3
45 CPUCLK2
44
V_SSCPU
43
V_DDCPU
42 CPUCLK1
41 _CPUCLK0
40
V_SSCPU
39
AV_DD
38
AV_SS
37 ^PCI_STOP
36 CPU_STOP
35 _{PWR_DWN}
34 SPREAD
33 SEL1
32 SEL0
31
V_DDUSB
30 USBCLK
29
V_SSUSB
Rev 1.0, November 25, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:[phone] Fax:[phone]
Page 1 of 10
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