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| AM70PDLI27BDH Datasheet, PDF (94/128 Pages) SPANSION – Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) | |||
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Addresses
(x16)
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
Addresses
(x16)
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
ADVANCE INFORMATION
Table 6. System Interface String
Data
0027h
0036h
0000h
0000h
0007h
0007h
000Ah
0000h
0001h
0005h
0004h
0000h
Description
VCC Min. (write/erase)
D7âD4: volt, D3âD0: 100 millivolt
VCC Max. (write/erase)
D7âD4: volt, D3âD0: 100 millivolt
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 7. Device Geometry Definition
Data
0017h
0002h
0000h
0005h
0000h
0001h
007Fh
0000h
0000h
0001h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Device Size = 2N byte
Description
Flash Device Interface description (refer to CFI publication 100)
Max. number of byte in multi-byte write = 2N
(00h = not supported)
Number of Erase Block Regions within device (01h = uniform device, 02h = boot device)
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
Erase Block Region 2 Information (refer to CFI publication 100)
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
92
Am70PDL127BDH/Am70PDL129BDH
November 25, 2003
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