S71PL512ND0 Datasheet, PDF (9/90 Pages) SPANSION – Two S29PL256N Devices (32 M x 16-Bit) CMOS 3.0-Volt only Simultaneous Read/Write, Page-Mode Flash Memory

Preliminary
2 Input/Output Descriptions and Logic Symbol
Table 2.1 identifies the input and output package connections provided on the device.
Table 2.1 Input/Output Descriptions
Symbol
Type
Description
A23– A0
Input
Address Inputs (common)
DQ15 – DQ0 I/O
16-bit data inputs/outputs (common)
F1-CE#
Input
Chip Enable (Flash 1)
F2-CE#
Input
Chip Enable (Flash 2)
R-CE1#
Input
Chip Enable 1 (pSRAM)
R-CE2
Input
Chip Enable 2 (pSRAM)
OE#
Input
Output Enable input
WE#
Input
Write Enable
RY/BY#
Output
Ready/Busy Output (Flash 1)
UB#
Input
Upper Byte Control (pSRAM)
LB#
Input
Lower Byte Control (pSRAM)
RESET#
Input
Hardware reset pin, Active Low (Flash 1)
WP#/ACC Input
Hardware Write Protect/Acceleration pin (Flash)
F-V_CCf
Supply
Flash 3.0 volt-only single power supply (see Product Selctor Guide for speed options and
voltage supply tolerances)
R-V_CC
V_SS
NC
Supply
pSRAM Power Supply
Supply
Device ground (common)
Not connected Pin Not Connected Internally
24
A23–A0
F1-CE#
16
DQ15–DQ0
F2-CE#
R-CE1#
R-CE2
OE#
WE#
WP #/ACC
R Y/BY#
RES ET#
UB#
LB#
December 6, 2005 S71PL512ND0_00_A2
S71PL512ND0 MirrorBit™ Flash Family
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