S25FL128SAGMFIR01 Datasheet, PDF (88/153 Pages) SPANSION – MirrorBit® Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

Data Sheet
 As part of the power up reset, hardware reset, or command reset process the AutoBoot feature
automatically starts a read access from a pre-specified address. At the time the reset process is
completed, the device is ready to deliver code from the starting address. The host memory controller only
needs to drive CS# signal from high to low and begin toggling the SCK signal. The S25FL128S and
S25FL256S device will delay code output for a pre-specified number of clock cycles before code streams
out.
– The Auto Boot Start Delay (ABSD) field of the AutoBoot register specifies the initial delay if any is
needed by the host.
– The host cannot send commands during this time.
– If ABSD = 0, the maximum SCK frequency is 50 MHz.
– If ABSD > 0, the maximum SCK frequency is 133 MHz if the QUAD bit CR1[1] is 0 or 104 MHz if the
QUAD bit is set to 1.
 The starting address of the boot code is selected by the value programmed into the AutoBoot Start
Address (ABSA) field of the AutoBoot Register which specifies a 512-byte boundary aligned location; the
default address is 00000000h.
– Data will continuously shift out until CS# returns high.
 At any point after the first data byte is transferred, when CS# returns high, the SPI device will reset to
standard SPI mode; able to accept normal command operations.
– A minimum of one byte must be transferred.
– AutoBoot mode will not initiate again until another power cycle or a reset occurs.
 An AutoBoot Enable bit (ABE) is set to enable the AutoBoot feature.
The AutoBoot register bits are non-volatile and provide:
 The starting address (512-byte boundary), set by the AutoBoot Start Address (ABSA). The size of the
ABSA field is 23 bits for devices up to 32-Gbit.
 The number of initial delay cycles, set by the AutoBoot Start Delay (ABSD) 8-bit count value.
 The AutoBoot Enable.
If the configuration register QUAD bit CR1[1] is set to 1, the boot code will be provided 4 bits per cycle in the
same manner as a Read Quad Out command. If the QUAD bit is 0 the code is delivered serially in the same
manner as a Read command.
Figure 10.15 AutoBoot Sequence (CR1[1]=0)
CS#
SCK
SI
SO
0 - - - - - - n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9
Wait State
tWS
Don’t care or High Impedance
High Impedance
76
MSB
DATA OUT 1
54321
DATA OUT 2
07
MSB
88
S25FL128S and S25FL256S
S25FL128S_256S_00_05 July 12, 2012