MB9B110T Datasheet, PDF (88/129 Pages) SPANSION – This document states the current technical specifications regarding

DataSheet
 Separate Bus Access Asynchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol Pin name Conditions
Value
Min
Max
Unit
MOEX
Min pulse width
t_OEW
MOEX
Vcc ≥ 4.5 V
MCLK×n-3
-
ns
Vcc < 4.5 V
MCSX ↓ → Address
output delay time
t_{CSL – AV}
MCSX[7:0],
MAD[24:0]
Vcc ≥ 4.5 V
Vcc < 4.5 V
-9
-12
+9
ns
+12
MOEX ↑ →
Address hold time
t_{OEH - AX}
MOEX,
MAD[24:0]
Vcc ≥ 4.5 V
Vcc < 4.5 V
0
MCLK×m+9 _ns
MCLK×m+12
MCSX ↓ →
MOEX ↓ delay time
t_{CSL - OEL}
MOEX,
Vcc ≥ 4.5 V MCLK×m-9 MCLK×m+9 _ns
Vcc < 4.5 V MCLK×m-12 MCLK×m+12
MOEX ↑ →
MCSX ↑ time
t_{OEH - CSH}
MCSX[7:0]
Vcc ≥ 4.5 V
Vcc < 4.5 V
0
MCLK×m+9 _ns
MCLK×m+12
MCSX ↓ →
MDQM ↓ delay time
t_{CSL - RDQML}
MCSX,
MDQM[1:0]
Vcc ≥ 4.5 V MCLK×m-9 MCLK×m+9 _ns
Vcc < 4.5 V MCLK×m-12 MCLK×m+12
Data set up →
MOEX ↑ time
t_{DS - OE}
MOEX,
Vcc ≥ 4.5 V
MADATA[15:0] Vcc < 4.5 V
20
38
-
ns
-
MOEX ↑ →
Data hold time
t_{DH - OE}
MOEX,
Vcc ≥ 4.5 V
MADATA[15:0] Vcc < 4.5 V
0
-
ns
MWEX
Min pulse width
t_WEW
MWEX
Vcc ≥ 4.5 V _MCLK×n-3
-
ns
Vcc < 4.5 V
MWEX ↑ → Address
output delay time
t_{WEH - AX}
MWEX,
MAD[24:0]
Vcc ≥ 4.5 V
Vcc < 4.5 V
0
MCLK×m+9 _ns
MCLK×m+12
MCSX ↓ →
MWEX ↓ delay time
t_{CSL - WEL}
MWEX,
Vcc ≥ 4.5 V MCLK×n-9 MCLK×n+9 _ns
Vcc < 4.5 V MCLK×n-12 MCLK×n+12
MWEX ↑ →
MCSX ↑ delay time
t_{WEH - CSH}
MCSX[7:0]
Vcc ≥ 4.5 V
Vcc < 4.5 V
0
MCLK×m+9 _ns
MCLK×m+12
MCSX ↓ →
MDQM ↓ delay time
t_CSL-WDQML
MCSX,
MDQM[1:0]
Vcc ≥ 4.5 V MCLK×n-9 MCLK×n+9 _ns
Vcc < 4.5 V MCLK×n-12 MCLK×n+12
MCSX ↓ →
Data output time
t_{CSL - DV}
MCSX,
MADATA[15:0]
Vcc ≥ 4.5 V
Vcc < 4.5 V
MCLK-9
MCLK-12
MCLK+9
MCLK+12
ns
MWEX ↑ →
Data hold time
t_{WEH - DX}
MWEX,
MADATA[15:0]
Vcc ≥ 4.5 V
Vcc < 4.5 V
0
MCLK×m+9 _ns
MCLK×m+12
Note: When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16)
January 31, 2014, MB9B110T-DS706-00016-3v0-E
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