IRA-E700 Datasheet, PDF (81/86 Pages) Murata Manufacturing Co., Ltd. – Dual Type Pyroelectric Infrared Sensor

Data Sheet (Advance Information)
RA = Read Address.
RD = Read Data.
PA = Program Address. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK, whichever occurs first.
PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first.
SA = Sector Address. NS128P = A22 – A14, NS256P = A23 – A14.
BA = Bank Address. NS128P = A22 – A20, and A19; NS256P = A23 – A20.
CR = Configuration Register data bits D15 – D0.
PWD3 – PWD0 = Password Data. PD3 – PD0 present four 16 bit combinations that represent the 64-bit Password
PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity.
PWD = Password Data.
RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0, if unprotected, DQ0 = 1.
WBL = Write Buffer Location. Address must be within the same write buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes
1. See Table 6.1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of
the configuration register verify and password verify commands, and any cycle reading at RD(0) and RD(1).
4. Data bits DQ15 – DQ8 are don’t care in command sequences, except for RD, PD, WD, PWD, and PWD3 – PWD0.
5. Unless otherwise noted, address bits Amax – A14 are don’t cares.
6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The
system must write the reset command to return the device to reading array data.
7. No unlock or command cycles required when bank is reading array data.
8. The data is 0000h for an unlocked sector and 0001h for a locked sector.
9. The Exit command must be issued to reset the device into read mode, otherwise the device hangs.
10. Data is always output at the rising edge of clock.
11.1
Common Flash Memory Interface
The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows specific vendor-specified soft-ware algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC ID-independent, and forward-compatible
and backward-compatible for the specified flash device families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address
(BA)55h any time the device is ready to read array data. The system can read CFI information at the
addresses given in Tables 11.3 – 11.6) within that bank. All reads outside of the CFI address range, within the
bank, returns non-valid data. Reads from other banks are allowed, writes are not. To terminate reading CFI
data, the system must write the reset command.
The following is a C source code example of using the CFI Entry and Exit functions. Refer to the Spansion
Low Level Driver User’s Guide (www.spansion.com) for general information on Spansion Flash memory
software development guidelines.
/* Example: CFI Entry command */
*( (UINT16 *)bank_addr + 0x0055 = 0x0098; /* write CFI entry command
*/
/* Example: CFI Exit command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00F0; /* write cfi exit command
*/
For further information, please refer to the CFI Specification (see JEDEC publications JEP137-A and
JESD68.01and CFI Publication 100). Please contact your sales office for copies of these documents.
February 20, 2007 S29NS-P_00_A1
S29NS-P MirrorBit^TM Flash Family
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