MB9B410R Datasheet, PDF (8/121 Pages) SPANSION – This document states the current technical specifications regarding

DataSheet
 Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down counters.
Operation mode is selectable from the followings for each channel.
・ Free-running
・ Periodic (=Reload)
・ One-shot
 Watch Counter
The Watch counter is used for wake up from power consumption mode.
Interval timer: up to 64 s (Max) @ Sub Clock : 32.768 kHz
 External Interrupt Controller Unit
・ Up to 16 external interrupt input pin
・ Include one non-maskable interrupt (NMI)
 Watchdog Timer (Two channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low-speed internal CR oscillator. Therefore, "Hardware"
watchdog is active in any power consumption mode except Stop mode.
 CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
・ CCITT CRC16 Generator Polynomial: 0x1021
・ IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
 Clock and Reset
[Clocks]
Five clock sources (2 external oscillators, 2 internal CR oscillator, and Main PLL) that are dynamically
selectable.
・ Main Clock:
・ Sub Clock:
・ High-speed internal CR Clock:
・ Low-speed internal CR Clock:
・ Main PLL Clock
[Resets]
・ Reset requests from INITX pin
・ Power on reset
・ Software reset
・ Watchdog timers reset
・ Low-voltage detector reset
・ Clock supervisor reset
4 MHz to 48 MHz
32.768 kHz
4 MHz
100 kHz
 Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.
・ External OSC clock failure (clock stop) is detected, reset is asserted.
・ External OSC frequency anomaly is detected, interrupt or reset is asserted.
March 11, 2015, MB9B410R-DS706-00026-3v0-E
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