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MB9B110R Datasheet, PDF (8/121 Pages) SPANSION – This document states the current technical specifications regarding | |||
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DataSheet
ï¬ Watch Counter
The Watch counter is used for wake up from power consumption mode.
Interval timer: up to 64 s (Max) @ Sub Clock : 32.768 kHz
ï¬ External Interrupt Controller Unit
ã» Up to 16 external interrupt input pin
ã» Include one non-maskable interrupt (NMI)
ï¬ Watchdog Timer (Two channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low-speed internal CR oscillator. Therefore, "Hardware"
watchdog is active in any power consumption mode except Stop mode.
ï¬ CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
ã» CCITT CRC16 Generator Polynomial: 0x1021
ã» IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
ï¬ Clock and Reset
[Clocks]
Five clock sources (2 external oscillators, 2 internal CR oscillator, and Main PLL) that are dynamically
selectable.
ã» Main Clock:
ã» Sub Clock:
ã» High-speed internal CR Clock:
ã» Low-speed internal CR Clock:
ã» Main PLL Clock
[Resets]
ã» Reset requests from INITX pin
ã» Power on reset
ã» Software reset
ã» Watchdog timers reset
ã» Low-voltage detector reset
ã» Clock supervisor reset
4 MHz to 48 MHz
32.768 kHz
4 MHz
100 kHz
ï¬ Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.
ã» External OSC clock failure (clock stop) is detected, reset is asserted.
ã» External OSC frequency anomaly is detected, interrupt or reset is asserted.
March 11, 2015, MB9B110R-DS706-00028-3v0-E
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