AM49PDL127BH Datasheet, PDF(78/86 Page) SPANSION – 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2 M x 16-Bit) CMOS

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AM49PDL127BH Datasheet, PDF (78/86 Pages) SPANSION – 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2 M x 16-Bit) CMOS

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ADVANCE INFORMATION

pSRAM AC CHARACTERISTICS

Read Cycle

Addresses

A0 to A2

Addresses

A3 to A20

tPM

tRC

tPC

CE#1

CE2

Fixed High

OE#

WE#

LB#, UB#

DOUT

I/O1 to 16

tOE

tBA

tOEE

tBE

tAOH

tCOE

tCO

tACC

DOUT

tAA

tAOH

DOUT

tAA

Maximum 8 words

tOD

tBD

tOH

DOUT

tODO

Figure 28. Page Read Timing

Notes:

1. tOD, tODo, tBD, and tODW are defined as the time at which

the outputs achieve the open circuit condition and are not

referenced to output voltage levels.

3. If CE#f1, LB#, or UB# goes low at the same time or after

WE# goes low, the outputs will remain at high impedance.

2. If CE#f1, LB#, or UB# goes low at the same time or before

WE# goes high, the outputs will remain at high impedance.

Am49PDL127BH/Am49PDL129BH

December 16, 2003

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