S29GL-P_07 Datasheet, PDF (75/77 Pages) SPANSION – 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology

Data Sheet (Preliminary)
13. Advance Information on S29GL-R 65 nm MirrorBit Hardware
Reset (RESET#) and Power-up Sequence
Table 13.1 Hardware Reset (RESET#)
Parameter
Description
t_RPH
t_RP
t_RH
RESET# Low to CE# Low
RESET# Pulse Width
Time between RESET# (high) and CE# (low)
Note
CE#, OE# and WE# must be at logic high during Reset Time.
Limit
Min
Min
Min
Time
Unit
35
µs
200
ns
200
ns
Figure 13.1 Reset Timings
RESET#
t_RP
t_RH
t_RPH
CE#
Note
The sum of t_RP and t_RH must be equal to or greater than t_RPH.
Table 13.2 Power-Up Sequence Timings
Parameter
Description
Limit
Time
Unit
t_VCS
t_VIOS
t_RPH
t_RP
t_RH
V_CC Setup Time to first access
V_IO Setup Time to first access
RESET# Low to CE# Low
RESET# Pulse Width
Time between RESET# (high) and CE# (low)
Min
300
µs
Min
300
µs
Min
35
µs
Min
200
ns
Min
200
ns
Notes
1. V_IO < V_CC + 200 mV.
2. V_IO and V_CC ramp must be in sync during power-up. If RESET# is not stable for 500 µs, the following conditions may occur: the device
does not permit any read and write operations, valid read operations return FFh, and a hardware reset is required.
3. Maximum V_CC power up current is 20 mA (RESET# =V_IL).
Figure 13.2 Power-On Reset Timings
V_CC
V _IO
RESET#
t _VIOS
t _VCS
CE#
Note
The sum of t_RP and t_RH must be equal to or greater than t_RPH.
t _RP
t _RH
t _RPH
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit^® Flash Family
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