S29CD-J_12 Datasheet, PDF (71/81 Pages) SPANSION – 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-Only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O™

Data Sheet
18.8 Erase and Programming Performance
Table 18.7 Erase and Programming Performance
Parameter
Typ
(Note 1)
Max
(Note 2)
Unit
Comments
Sector Erase Time
Chip Erase Time
0.5
16 Mb = 23
32 Mb = 46
5
16 Mb = 230
32 Mb = 460
s
Excludes 00h programming prior to erasure
s ^{(Note 4)}
Double Word Program Time
8
130
µs
Accelerated Double Word Program Time
8
130
µs
Accelerated Chip Program Time
16 Mb = 5
32 Mb = 10
16 Mb = 50
32 Mb = 100
s ^{Excludes system level overhead (Note 5)}
Chip Program Time, x32 (Note 3)
16 Mb = 12
32 Mb = 24
16 Mb = 120
32 Mb = 240
s
Notes
1. Typical program and erase times assume the following conditions: 25°C, 2.5V V_CC, 100K cycles. Additionally, programming typicals assume checkerboard
pattern.
2. Under worst case conditions of 145°C, V_CC = 2.5V, 1M cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 20.1 and Table 20.2 for further
information on command definitions.
6. PPBs have a program/erase cycle endurance of 100 cycles.
7. Guaranteed cycles per sector is 100K minimum.
18.9
PQFP and Fortified BGA Pin Capacitance
Table 18.8 PQFP and Fortified BGA Pin Capacitance
Parameter Symbol
C_IN
C_OUT
C_IN2
Notes
1. Sampled, not 100% tested.
2. Test conditions T_A = 25°C, f = 1.0 MHz.
Parameter Description
Input Capacitance
Output Capacitance
Control Pin Capacitance
Test Setup
V_IN = 0
V_OUT = 0
V_IN = 0
Typ Max Unit
6
7.5
pF
8.5 12
pF
7.5
9
pF
October 11, 2012 S29CD-J_CL-J_00_B7
S29CD-J and S29CL-J Flash Family
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