S71PL254 Datasheet, PDF (62/196 Pages) SPANSION – STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM

Advance Information
START
RESET# =
V_IH or V_ID
Wait 1 µs
Write 60h to
any address
Write 40h to SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
Read from SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
If data = 00h,
SecSi Sector is
unprotected.
If data = 01h,
SecSi Sector is
protected.
Remove V_IH or V_ID
from RESET#
Write reset
command
SecSi Sector
Protect Verify
complete
Figure 3. Secured Silicon Sector Protect Verify
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes. In addition, the following
hardware data protection measures prevent accidental erasure or programming,
which might otherwise be caused by spurious system level signals during V_CC
power-up and power-down transitions, or from system noise.
Low V_CC Write Inhibit
When V_CC is less than V_LKO, the device does not accept any write cycles. This pro-
tects data during V_CC power-up and power-down. The command register and all
internal program/erase circuits are disabled, and the device resets to the read
mode. Subsequent writes are ignored until V_CC is greater than V_LKO. The system
must provide the proper signals to the control pins to prevent unintentional writes
when V_CC is greater than V_LKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE#, CE#, or WE# do not initiate a
write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V_IL, CE# = V_IH or WE# =
V_IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V_IL and OE# = V_IH during power up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automatically
reset to the read mode on power-up.
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S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004