AM41DL3208G Datasheet, PDF (60/65 Pages) SPANSION – Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

AC CHARACTERISTICS
Address
CE1#s
CE2s
UB#s, LB#s
WE#
Data In
Data Out
PRELIMINARY
t_WC
t_AS (See Note 2 ) _tCW
(See Note 3)
t_AW
t_WR (See Note 4)
High-Z
t_BW
t_WP
(See Note 5)
t_DW
t_DH
Data Valid
High-Z
Notes:
1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing.
2. t_CW is measured from CE1#s going low to the end of write.
3. t_WR is measured from the end of write to the address change. t_WR applied in case a write ends as CE1#s or WE# going high.
4. t_AS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (t_WP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t_WP is measured from the beginning of write
to the end of write.
Figure 31. SRAM Write Cycle—CE1#s Control
February 13, 2002
Am41DL3208G
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