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AM42BDS640AG Datasheet, PDF (51/72 Pages) Advanced Micro Devices – 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM
PRELIMINARY
AC CHARACTERISTICS
Erase/Program Operations
Parameter
JEDEC
Standard Description
All Speed
Options Unit
tAVAV
tAVWL
tWC
Write Cycle Time (Note 1)
tAS
Address Setup Time Synchronous
(Note 2)
Asynchronous
Min
80
ns
5
Min
ns
0
tWLAX
tAH
Address Hold Time
(Note 2)
Synchronous
Asynchronous
7
Min
ns
45
tDVWH
tWHDX
tGHWL
tWHEH
tWLWH
tWHWL
tWHWH1
tWHWH1
tWHWH2
tACS
tACH
tDS
tDH
tGHWL
tCAS
tCH
tWP
tWPH
tSR/W
tWHWH1
tWHWH1
tWHWH2
Address Setup Time to CLK (Note 2)
Address Hold Time to CLK (Note 2)
Data Setup Time
Data Hold Time
Read Recovery Time Before Write
CE# Setup Time to AVD#
CE# Hold Time
Write Pulse Width
Write Pulse Width High
Latency Between Read and Write Operations
Programming Operation (Note 3)
Accelerated Programming Operation (Note 3)
Sector Erase Operation (Notes 3, 4)
Chip Erase Operation (Notes 3, 4)
Min
5
ns
Min
7
ns
Min
45
ns
Min
0
ns
Min
0
ns
Min
0
ns
Min
0
ns
Min
50
ns
Min
30
ns
Min
0
ns
Typ
8
µs
Typ
2.5
µs
0.2
Typ
sec
26.8
tELWL
tVID
tVIDS
tVCS
tCSW1
tCSW2
tCHW
tCS
tAVSW
tAVHW
tAVHC
tAVDP
VACC Rise and Fall Time
VACC Setup Time (During Accelerated Programming)
VCC Setup Time
Clock Setup Time to WE# (Asynchronous)
Clock Setup Time to WE# (Synchronous)
Clock Hold Time from WE#
CE# Setup Time to WE#
AVD# Setup Time to WE#
AVD# Hold Time to WE#
AVD# Hold Time to CLK
AVD# Low Time
Min
500
ns
Min
1
µs
Min
50
µs
Min
5
ns
Min
1
ns
Min
1
ns
Min
0
ns
Min
5
ns
Min
5
ns
Min
5
ns
Min
12
ns
Notes:
1. Not 100% tested.
2. In asynchronous timing, addresses are latched on the falling edge of WE#. In synchronous mode, addresses are latched on the
first of either the rising edge of AVD# or the active edge of CLK.
3. See the “Flash Erase And Programming Performance” section for more information.
4. Does not include the preprogramming time.
50
Am42BDS640AG
November 1, 2002