S25FL116K Datasheet, PDF (49/79 Pages) SPANSION – 16-Mbit CMOS 3.0-Volt Flash Non-Volatile Memory Serial Peripheral Interface with Multi-I/O and Industrial and Automotive Temperature

Data Sheet (Preliminary)
7.4.8
Status Register Protect (SRP1, SRP0)
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read / write bits in the Status Register
(SR2[0] and SR1[7]). The SRP bits control the method of write protection: software protection, hardware
protection, power supply lock-down, or one time programmable (OTP) protection.
Table 7.9 Status Register Protection Bits
SRP1 SRP0 WP#
Status Register
Description
0
0
X
Software Protection
WP# pin has no control. SR1 and SR2 can be written to after a
Write Enable command, WEL=1. [Factory Default]
0
1
0
Hardware Protected
When WP# pin is low the SR1 and SR2 are locked and can not
be written.
0
1
1
Hardware Unprotected
When WP# pin is high SR1 and SR2 are unlocked and can be
written to after a Write Enable command, WEL=1.
1
0
X
Power Supply Lock-
Down
SR1 and SR2 are protected and can not be written to again until
the next power-down, power-up cycle. (1)
1
1
X One Time Program (2) SR1 and SR2 are permanently protected and can not be written.
Notes:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.
2. The One Time Program feature is available upon special order. Please contact Spansion for details.
3. Busy, WEL, and SUS (SR1[1:0] and SR2[7]) are volatile read only status bits that are never affected by the Write Status Registers
command.
4. The non-volatile version of CMP, QE, SRP1, SRP0, SEC, TB, and BP2-BP0 (SR2[6,1,0] and SR1[6:2]) bits and the OTP LB3-LB0 bits are
not writable when protected by the SRP bits and WP# as shown in the table. The non-volatile version of these Status Register bits are
selected for writing when the Write Enable (06h) command precedes the Write Status Registers (01h) command.
5. The volatile version of CMP, QE, SRP1, SRP0, SEC, TB, and BP2-BP0 (SR2[6,1,0] and SR1[6:2]) bits are not writable when protected by
the SRP bits and WP# as shown in the table. The volatile version of these Status Register bits are selected for writing when the Write
Enable for volatile Status Register (50h) command precedes the Write Status Registers (01h) command. There is no volatile version of
the LB3-LB0 bits and these bits are not affected by a volatile Write Status Registers command.
6. The volatile SR3 bits are not protected by the SRP bits and may be written at any time by volatile (50h) Write Enable command preceding
the Write Status Registers (01h) command.
7.4.9
Erase / Program Suspend Status (SUS)
The Suspend Status bit is a read only bit in the status register (SR2[7]) that is set to 1 after executing an
Erase / Program Suspend (75h) command. The SUS status bit is cleared to 0 by Erase / Program Resume
(7Ah) command as well as a power-down, power-up cycle.
7.4.10
Security Register Lock Bits (LB3, LB2, LB1, LB0)
The Security Register Lock Bits (LB3, LB2, LB1, LB0) are non-volatile One Time Program (OTP) bits in
Status Register (SR2[5:2]) that provide the write protect control and status to the Security Registers. The
default state of LB[3:1] is 0, Security Registers 1 to 3 are unlocked. LB[3:1] can be set to 1 individually using
the Write Status Registers command. LB[3:1] are One Time Programmable (OTP), once it’s set to 1, the
corresponding 256-byte Security Register will become read-only permanently.
Security Register 0 is programmed with the SFDP parameters and LB0 is programmed to 1 by Spansion.
7.4.11
Quad Enable (QE)
The Quad Enable (QE) bit is a non-volatile read / write bit in the Status Register (SR2[1]) that allows Quad
SPI operation. When the QE bit is set to a 0 state (factory default), the WP# pin and HOLD# are enabled.
When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and WP# and HOLD# functions are
disabled.
Note: If the WP# or HOLD# pins are tied directly to the power supply or ground during standard SPI or Dual
SPI operation, the QE bit should never be set to a 1.
November 6, 2013 S25FL116K_00_06
S25FL116K
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