S29CD-G Datasheet, PDF (48/87 Pages) SPANSION – 32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O

Preliminary
Unlock Bypass Chip Erase Command
The Unlock Bypass Chip Erase command is a 2-cycle command that consists of the erase setup
command (80h) and the actual chip erase command (10h). This command does not require the
two-cycle unlock sequence since the Unlock Bypass command was previously issued. Unlike the
standard erase command, there is no Unlock Bypass Erase Suspend or Erase Resume commands.
To return back to standard read operations, the Unlock Bypass Reset command must be issued.
The Unlock Bypass Program Command is ignored if the Secured Silicon sector is enabled.
Unlock Bypass CFI Command
The Unlock Bypass CFI command is available for PROM programmers and target systems to read
the CFI codes while in Unlock Bypass mode. See Common Flash Interface (CFI) Command on
page 50 for specific CFI codes.
To return back to standard read operations, the Unlock Bypass Reset command must be issued.
The Unlock Bypass Program Command is ignored if the Secured Silicon sector is enabled.
Unlock Bypass Reset Command
The Unlock Bypass Reset command places the device in standard read/reset operating mode.
Once executed, normal read operations and user command sequences are available for execution.
The Unlock Bypass Program Command is ignored if the Secured Silicon sector is enabled.
Chip Erase Command
The Chip Erase command is used to erase the entire flash memory contents of the chip by issuing
a single command. Chip erase is a six-bus cycle operation. There are two unlock write cycles, fol-
lowed by writing the erase set-up command. Two more unlock write cycles are followed by the
chip erase command. Chip erase does not erase protected sectors.
The chip erase operation initiates the Embedded Erase algorithm, which automatically prepro-
grams and verifies the entire memory to an all zero pattern prior to electrical erase. The system
is not required to provide any controls or timings during these operations. Note that a hardware
reset immediately terminates the programming operation. The command sequence should be
reinitiated once that bank returns to reading array data, to ensure data integrity.
The Embedded Erase algorithm erase begins on the rising edge of the last WE# or CE# pulse
(whichever occurs first) in the command sequence. The status of the erase operation is deter-
mined three ways:
„ Data# polling of the DQ7 pin (See DQ7: Data# Polling on page 56)
„ Checking the status of the toggle bit DQ6 (See DQ6: Toggle Bit I on page 58)
„ Checking the status of the RY/BY# pin (See RY/BY#: Ready/Busy# on page 56)
Once erasure begins, only the Erase Suspend command is valid. All other commands are ignored.
When the Embedded Erase algorithm is complete, the device returns to reading array data, and
addresses are no longer latched. Note that an address change is required to begin read valid array
data.
Figure 5 on page 48 illustrates the Embedded Erase Algorithm. See the Erase/Program
Operations on page 73 for parameters, and Figure 21 and Figure 22 for timing diagrams.
Sector Erase Command
The Sector Erase command is used to erase individual sectors or the entire flash memory con-
tents. Sector erase is a six-bus cycle operation. There are two unlock write cycles, followed by
writing the erase set-up command. Two more unlock write cycles are then followed by the erase
command (30h). The sector address (any address location within the desired sector) is latched
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S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005