S25FL064P0XBHIS30 Datasheet, PDF(48/67 Page) SPANSION – 64-Mbit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus

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S25FL064P0XBHIS30 Datasheet, PDF (48/67 Pages) SPANSION – 64-Mbit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus

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Data Sheet

9.20.1

Release from Deep Power-Down and Read Electronic Signature (RES)

The device features an 8-bit Electronic Signature, which can be read using the RES command. See

Figure 9.24 and Table 9.1 on page 23 for the command sequence and signature value. The Electronic

Signature is not to be confused with the identification data obtained using the RDID command. The device

offers the Electronic Signature so that it can be used with previous devices that offered it; however, the

Electronic Signature should not be used for new designs, which should read the RDID data instead.

After the host system drives CS# low, it must write the RES command followed by 3 dummy bytes to SI (each

bit is latched on SI during the rising edge of SCK). The Electronic Signature is then output on SO; each bit is

shifted out on the falling edge of SCK. The RES operation is terminated by driving CS# high after the

Electronic Signature is read at least once. Additional clock cycles on SCK with CS# low cause the device to

output the Electronic Signature repeatedly.

When CS# is driven high, the device transitions from DP mode to the standby mode after a delay of tRES, as

previously described. The RES command always provides access to the Electronic Signature of the device

and can be applied even if DP mode has not been entered.

Any RES command issued while an erase, program, or Write Registers operation is in progress not executed,

and the operation continues uninterrupted.

Figure 9.24 Release from Deep Power-Down and RES Command Sequence

CS#

SCK

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

Instruction

High Impedance

3 Dummy

Bytes

23 22 21

MSB

321 0

Electonic ID

7 6543 210

MSB

Deep Power-Down Mode

t RES

Standby Mode

9.21

Clear Status Register (CLSR)

The Clear Status Register command resets bit SR5 (Erase Fail Flag) and bit SR6 (Program Fail Flag). It is not

necessary to set the WEL bit before the Clear SR Fail Flags command is executed. The WEL bit will be

unchanged after this command is executed.

Figure 9.25 Clear Status Register (CLSR) Instruction Sequence

CS#

SCK

01234567

Instruction

S25FL064P

S25FL064P_00_08 January 29, 2013

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