AM49DL320BG Datasheet, PDF (43/64 Pages) SPANSION – Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous

PRELIMINARY
FLASH AC CHARACTERISTICS
Read-Only Operations
Parameter
Speed
JEDEC Std. Description
Test Setup
70
85 Unit
t_AVAV
t_RC Read Cycle Time (Note 1)
Min
70
85
ns
t_AVQV
t_ACC Address to Output Delay
CE#f, OE# = V_IL Max
70
85
ns
t_ELQV
t_CE Chip Enable to Output Delay
OE# = V_IL
Max
70
85
ns
t_GLQV
t_OE Output Enable to Output Delay
Max
30
40
ns
t_EHQZ
t_DF Chip Enable to Output High Z (Notes 1, 3)
Max
30
35
ns
t_GHQZ
t_DF Output Enable to Output High Z (Notes 1, 3)
Max
30
ns
t_AXQX
t_OH
Output Hold Time From Addresses, CE#f or
OE#, Whichever Occurs First
Min
0
ns
t_OEH
Output Enable Hold Time
(Note 1)
Read
Toggle and
Data# Polling
Min
0
ns
Min
10
ns
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 15 for test specifications
3. Measurements performed by placing a 50Ω termination on the data pin with a bias of V_CC/2. The time from OE# high to the
data bus driven to V_CC/2 is taken as t_DF
.
Addresses
CE#f
OE#
WE#
Outputs
t_RC
Addresses Stable
t_ACC
t_RH
t_RH
t_OEH
HIGH Z
t_OE
t_CE
t_DF
t_OH
Output Valid
HIGH Z
RESET#
RY/BY# _{0 V}
Figure 14. Read Operation Timings
42
Am49DL320BG
June 25, 2002