S70GL01GN00_07 Datasheet, PDF(41/83 Page) SPANSION – 1024 Megabit, 3.0 Volt-only Page Mode Flash Memory Featuring 110 nm MirrorBit™ Process Technology

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S70GL01GN00_07 Datasheet, PDF (41/83 Pages) SPANSION – 1024 Megabit, 3.0 Volt-only Page Mode Flash Memory Featuring 110 nm MirrorBit™ Process Technology

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Data Sheet

Addresses

(x16)

40h

41h

42h

43h

44h

45h

46h

47h

48h

49h

4Ah

4Bh

4Ch

4Dh

4Eh

4Fh

50h

Table 9. Primary Vendor-Specific Extended Query

Addresses

(x8)

Data

Description

80h

0050h

82h

0052h

Query-unique ASCII string âPRIâ

84h

0049h

86h

0031h

Major version number, ASCII

88h

0033h

Minor version number, ASCII

Address Sensitive Unlock (Bits 1-0)

8Ah

0010h

0 = Required, 1 = Not Required

Process Technology (Bits 7-2) 0100b = 110 nm MirrorBit

8Ch

0002h

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

8Eh

0001h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

90h

0000h

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

92h

0008h

Sector Protect/Unprotect scheme

0008h = Advanced Sector Protection

94h

0000h

Simultaneous Operation

00 = Not Supported, X = Number of Sectors in Bank

96h

0000h

Burst Mode Type

00 = Not Supported, 01 = Supported

98h

0002h

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

9Ah

00B5h

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

9Ch

00C5h

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

WP# Protection

9Eh

00xxh

04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top WP#

protect

Program Suspend

A0h

0001h

00h = Not Supported, 01h = Supported

Command Definitions

Writing specific address and data commands or sequences into the command

define the valid register command sequences. Writing incorrect address and data

values or writing them in the improper sequence may place the device in an un-

known state. A reset command is then required to return the device to reading

array data.

All addresses are latched on the falling edge of WE# or CE# (or CE2#), whichever

happens later. All data is latched on the rising edge of WE# or CE# (or CE2#),

whichever happens first. Refer to the AC Characteristics section for timing

diagrams.

May 21, 2007 S70GL01GN00_00_A2

S70GL01GN00 MirrorBitTM Flash

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