S70GL256M00 Datasheet, PDF (40/60 Pages) SPANSION – 256 Megabit (8 M x 32-Bit/16 M x 16-Bit) MirrorBit 3.0 Volt-only Uniform Sector Flash Memory with Versatile I/O Control

DATA SHEET
START
Read DQ7–DQ0
Read DQ7–DQ0
Toggle Bit
No
= Toggle?
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
DQ2 and DQ10: Toggle Bits II
The “Toggle Bits II” on DQ2 and DQ10, when used
with DQ6 and DQ14, indicate whether a particular
sector is actively erasing (that is, the Embedded Erase
algorithm is in progress), or whether that sector is
erase-suspended. Toggle Bits II are valid after the ris-
ing edge of the final WE# pulse in the command se-
quence.
DQ2 and DQ10 toggle when the system reads at ad-
dresses within those sectors that have been selected
for erasure. (The system may use either OE# or CE#
to control the read cycles.) But DQ2 and DQ10 cannot
distinguish whether the sector is actively erasing or is
erase-suspended. DQ6 and DQ14, by comparison, in-
dicate whether the device is actively erasing, or is in
Erase Suspend, but cannot distinguish which sectors
are selected for erasure. Thus, both status bits are re-
quired for sector and mode information. Refer to Table
12 to compare outputs for DQ2 and DQ10 and DQ6
and DQ14.
Figure 9 shows the toggle bit algorithm in flowchart
form, and the section “DQ2 and DQ10: Toggle Bits II”
explains the algorithm. See also the RY/BY#:
Ready/Busy# subsection. Figure 21 shows the toggle
bit timing diagram. Figure 22 shows the differences
between DQ2 and DQ10 and DQ6 and DQ14 in
graphical form.
Toggle Bit
No
= Toggle?
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note: The system should recheck the toggle bit even if
DQ5 and DQ13= “1” because the toggle bit may stop
toggling as DQ5 and DQ13 changes to “1.” See the
subsections on DQ6 and DQ14 and DQ2 and DQ10 for
more information.
Figure 9. Toggle Bit Algorithm
Reading Toggle Bits DQ6 and DQ14/DQ2
and DQ10
Refer to Figure 9 for the following discussion. When-
ever the system initially begins reading toggle bits sta-
tus, it must read DQ15–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bits are not toggling, the de-
vice has completed the program or erase operation.
The system can read array data on DQ15–DQ0 on the
following read cycle.
However, if after the initial two read cycles, the system
determines that one of the toggle bits are still toggling,
the system also should note whether the value of DQ5
and DQ13 is high (see the section on DQ5 and DQ13).
If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit
may have stopped toggling just as DQ5 and/or DQ13
went high. If the toggle bits are no longer toggling, the
device has successfully completed the program or
erase operation. If it is still toggling, the device did not
completed the operation successfully, and the system
must write the reset command to return to reading
array data.
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S70GL256M00
S70GL256M00_00_A1 October 31, 2006