S29NS-N_07 Datasheet, PDF (4/86 Pages) SPANSION – 256/128/64 Megabit (16/8/4M x 16-bit), CMOS 1.8 Volt-only Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory

Data Sheet (Advance Information)
1. General Description
The S29NS256N, S29NS128N and S29NS064N are 256 Mb, 128 Mb and 64Mb (respectively), 1.8 Volt-only,
Simultaneous Read/Write, Burst Mode Flash memory devices, organized as 16,777,216, 8,388,608, and
4,194,304 words of 16 bits each. These devices use a single V_CC of 1.70 to 1.95 V to read, program, and
erase the memory array. A 9.0-volt ACC, may be used for faster program performance if desired. These
devices can also be programmed in standard EPROM programmers.
The devices are offered at the following speeds:
Clock Speed
66 MHz
Burst Access (ns)
11.0
Synch. Initial Access (ns)
80
Asynch. Initial Access (ns)
80
Output Loading
30 pF
The devices operate within the temperature range of –25°C to
+85°C, and are offered in Very Thin FBGA packages.
1.1
Simultaneous Read/Write Operations with Zero Latency
The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space
into sixteen banks. The device allows a host system to program or erase in one bank, then immediately and
simultaneously read from another bank, with zero latency. This releases the system from waiting for the
completion of program or erase operations. The devices are structured as shown in the following tables:
Bank 0-14 Sectors
Quantity
Size
240
64 Kwords
240 Mb total
S29NS256N
Quantity
4
15
Bank 15 Sectors
16 Mb total
Size
16 Kwords
64 Kwords
Bank 0-14 Sectors
Quantity
Size
120
64 Kwords
120 Mb total
S29NS128N
Quantity
4
7
Bank 15 Sectors
8 Mb total
Size
16 Kwords
64 Kwords
Quantity
Bank 0-6 Sectors
Size
112
32 Kwords
56 Mbits
S29NS064N
Quantity
4
15
Bank 7 Sectors
8 Mbits
Size
8 Kwords
32 Kwords
The VersatileIO™ (V_IO) control allows the host system to set the voltage levels that the device generates at
its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the
V_CCQ pin.
The devices use Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to
control asynchronous read and write operations. For burst operations, the devices additionally require Ready
(RDY) and Clock (CLK). This implementation allows easy interface with minimal glue logic to
microprocessors/microcontrollers for high performance read operations.
The devices offer complete compatibility with the JEDEC 42.4 single-power-supply Flash command set
standard. Commands are written to the command register using standard microprocessor write timings.
Reading data out of the device are similar to reading from other Flash or EPROM devices.
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S29NS-N MirrorBit™ Flash Family
S29NS-N_00_A13 February 16, 2007