S25FL032P_12 Datasheet, PDF (30/69 Pages) SPANSION – 32-Mbit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus

Data Sheet
9.6
Quad I/O High Performance Read Mode (QIOR)
The Quad I/O High Performance Read instruction is similar to the Quad Output Read instruction, except that
it further improves throughput by allowing input of the address bits (A23-A0) using 4 bits per SCK via four
input pins (SI/IO0, SO/IO1, W#/ACC/IO2 and HOLD#/IO3), at a maximum frequency of 80 MHz.
The host system must first select the device by driving CS# low. The Quad I/O High Performance Read
command is then written to SI, followed by a 3-byte address (A23-A0) and a 1-byte Mode instruction, with four
bits latched on the rising edge of SCK. Note that four dummy clocks are required prior to the data input. Then
the memory contents, at the address that is given, are shifted out four bits at a time through IO0 (SI), IO1
(SO), IO2 (W#/ACC), and IO3 (HOLD#).
The Quad I/O High Performance Read command sequence is shown in Figure 9.7 and Table 9.1 on page 23.
The first address byte specified can start at any location of the memory array. The device automatically
increments to the next higher address after each byte of data is output. The entire memory array can
therefore be read with a single Quad I/O High Performance Read command. When the highest address is
reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely.
In addition, address jumps can be done without exiting the Quad I/O High Performance Mode through the
setting of the Mode bits (after the Address (A23-0) sequence, as shown in Figure 9.7). This added feature the
removes the need for the instruction sequence and greatly improves code execution (XIP). The upper nibble
(bits 7-4) of the Mode bits control the length of the next Quad I/O High Performance instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the Mode bits are DON'T
CARE (“x”). If the Mode bits equal Axh, then the device remains in Quad I/O High Performance Read Mode
and the next address can be entered (after CS# is raised high and then asserted low) without requiring the
EBh instruction opcode, as shown in Figure 9.8, thus eliminating eight cycles for the instruction sequence.
The following sequences will release the device from Quad I/O High Performance Read mode; after which,
the device can accept standard SPI instructions:
1. During the Quad I/O High Performance Instruction Sequence, if the Mode bits are any value other
than Axh, then the next time CS# is raised high and then asserted low the device will be released
from Quad I/O High Performance Read mode.
2. Furthermore, during any operation, if CS# toggles high to low to high for eight cycles (or less) and
data input (IO0, IO1, IO2, & IO3) are not set for a valid instruction sequence, then the device will be
released from Quad I/O High Performance Read mode.
It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock.
The read instruction can be terminated by driving the CS# pin to the logic high state. The CS# pin can be
driven high at any time during data output to terminate a read operation.
Figure 9.7 QUAD I/O High Performance Instruction Sequence
CS#
SCK
SI/IO0
SO/IO1
W#/ACC/IO2
HOLD#/IO3
0123456789
13 14 15 16 17 18 19 20 21 22 23 24 25 26
Instruction
Hi-Z
Hi-Z
Hi-Z
24 Bit
Address
IO’s Switches from Input to Output
20 16
21 17
22 18
23 19
*
0 40
40 ₄ 0 4
15 1
5151 5
26 2
6 26 2 6
3 73
*
73 73 7
*
*
*
Mode Bits DUMMY DUMMY Byte 1 Byte 2
*MSB
30
S25FL032P
S25FL032P_00_07 September 21, 2012