S34ML01G200TFI000 Datasheet, PDF (23/68 Pages) SPANSION – 1 Gb, 2 Gb, 4 Gb Densities: 4-bit ECC, x8 I/O and 3V VCC

Data Sheet (Advance Information)
On the other hand, if 31h is issued prior to completing the random access to the next page, the device will
stay busy as long as needed to complete random access to this page, transfer its contents into the cache
register, and trigger the random access to the following page.
To terminate the Read Cache operation, 3Fh command should be issued (see Figure 6.30 on page 52). This
command transfers data from the data register to the cache register without issuing next page read.
During the Read Cache operation, the device doesn't allow any other command except for 00h, 31h, 3Fh,
Read SR, or Reset (FFh). To carry out other operations, Read Cache must be terminated by the Read Cache
End command (3Fh) or the device must be reset by issuing FFh.
Read Status command (70h) may be issued to check the status of the different registers and the busy/ready
status of the cached read operations.
 The Cache-Busy status bit I/O6 indicates when the cache register is ready to output new data.
 The status bit I/O5 can be used to determine when the cell reading of the current data register contents is
complete.
Note: The Read Cache and Read Cache End commands reset the column counter, thus, when RE# is
toggled to output the data of a given page, the first output data is related to the first byte of the page (column
address 00h). Random Data Output command can be used to switch column address.
3.14
Cache Program — S34ML02G2 and S34ML04G2
Cache Program can be used with S34ML02G2 and S34ML04G2 devices to improve the program throughput
by programing data using the cache register. The cache program operation cannot cross a block boundary.
The cache register allows new data to be input while the previous data that was transferred to the data
register is programmed into the memory array.
After the serial data input command (80h) is loaded to the command register, followed by five cycles of
address, a full or partial page of data is latched into the cache register.
Once the cache write command (15h) is loaded to the command register, the data in the cache register is
transferred into the data register for cell programming. At this time the device remains in the Busy state for a
short time (t_CBSYW). After all data of the cache register is transferred into the data register, the device returns
to the Ready state and allows loading the next data into the cache register through another cache program
command sequence (80h-15h).
The Busy time following the first sequence 80h - 15h equals the time needed to transfer the data from the
cache register to the data register. Cell programming the data of the data register and loading of the next data
into the cache register is consequently processed through a pipeline model.
In case of any subsequent sequence 80h - 15h, transfer from the cache register to the data register is held off
until cell programming of current data register contents is complete; till this moment the device will stay in a
busy state (t_CBSYW).
Read Status commands (70h or 78h) may be issued to check the status of the different registers, and the
pass/fail status of the cached program operations.
 The Cache-Busy status bit I/O6 indicates when the cache register is ready to accept new data.
 The status bit I/O5 can be used to determine when the cell programming of the current data register
contents is complete.
 The cache program error bit I/O1 can be used to identify if the previous page (page N-1) has been
successfully programmed or not in a cache program operation. The status bit is valid upon I/O6 status bit
changing to 1.
 The error bit I/O0 is used to identify if any error has been detected by the program/erase controller while
programming page N. The status bit is valid upon I/O5 status bit changing to 1.
I/O1 may be read together with I/O0.
If the system monitors the progress of the operation only with R/B#, the last page of the target program
sequence must be programmed with Page Program Confirm command (10h). If the Cache Program
command (15h) is used instead, the status bit I/O5 must be polled to find out if the last programming is
finished before starting any other operation. See Table 3.2 on page 22 and Figure 6.31 on page 53 for more
details.
August 3, 2012 S34ML01G2_04G2_01
Spansion^® SLC NAND Flash Memory for Embedded
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