S25FL040A Datasheet, PDF (23/35 Pages) SPANSION – 4 Megabit CMOS 3.0 Volt Flash Memory with 50MHz SPI (Serial Peripheral Interface) Bus and Small Sector for Boot and Parameter Storage

Data Sheet (Preliminary)
CS#
Mode 3
SCK ^{Mode 0}
SI
Figure 9.9 Page Program (PP) Command Sequence
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31 32 33 34 35 36 37 38 39
Command
24-Bit Address
Data Byte 1
23 22 21
32 1 076 54 3 2 10
MSB
MSB
CS#
SCK
SI
40 41 42 43 44 45 46 47 48 49 50 51 52 ^{53 54 55}
Data Byte 2
Data Byte 3
765 4 32 107 6 5 4 32 10
MSB
MSB
Data Byte 256
765 43210
MSB
9.10
Sector Erase (SE)
The Sector Erase (SE) command sets all bits at all addresses within a specified sector to a logic 1. A WREN
command is required prior to writing the PP command.
The host system must drive CS# low, and then write the SE command plus three address bytes on SI. Any
address within the sector (see Table 7.1 on page 11) is a valid address for the SE command. CS# must be
driven low for the entire duration of the SE sequence. The command sequence is shown in Figure 9.10 and
Table 9.5.
The host system must drive CS# high after the device has latched the 8th bit of the SE command, otherwise
the device does not execute the command. The SE operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of t_SE. The Status Register may
be read to check the value of the Write In Progress (WIP) bit while the SE operation is in progress. The WIP
bit is 1 during the SE operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device does not execute an SE command that specifies a sector that is protected by the Block Protect
bits (BP2:BP0) (see Table 7.1 on page 11).
CS#
Mode 3
SCK
Mode 0
SI
SO ^Hi-Z
Figure 9.10 Sector Erase (SE) Command Sequence
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
Command
24-bit Address
23 22 21
MSB
3 21 0
August 31, 2006 S25FL040A_00_B0
S25FL040A
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