S71PL129JC0_06 Datasheet, PDF (145/153 Pages) SPANSION – Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM 128 Megabit (8M x 16-bit) CMOS3.0 Volt-only Simultaneous Operation, Page Mode Flash Memory

Advance Information
Timing Diagrams
tRC
tAX
ADDRESS
(A21-A3)
ADDRESS
(A2-A0)
ADDRESS VALID
tRC
tPRC
ADDRESS
VALID
tAA
ADDRESS
VALID
tPAA
CE1# _Low
tASO
tOE
tRC
tAx
ADDRESS VALID
tRC
tPRC
ADDRESS
VALID
tAA
ADDRESS
VALID
tPAA
OE#
tBA
LB#/UB#
DQ
tOLZ
tOH
tOH
tBLZ
(Output)
tOH
tOH
VALID DATA OUTPUT
(Normal Access)
VALID DATA OUTPUT
(Page Access)
Notes:
1. This timing diagram assumes CE2=H and WE#=H.
2. Either or both LB# and UB# must be Low when both CE1# and OE# are Low.
Figure 59. Read Timing #5 (Random and Page Address Access for 32M and 64M Only)
Write Timings
ADDRESS
CE1#
WE#
LB#, UB#
tAS
tAS
tAS
tOHCL
tWC
ADDRESS VALID
tCW
tWP
tBW
tWR
tAS
tCP
tWR
tAS
tWHP
tWR
tAS
tBHP
OE#
tDS
tDH
DQ
(Input)
Note: This timing diagram assumes CE2=H.
Figure 60.
VALID DATA INPUT
Write Timing #1 (Basic Timing)
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
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