S25FL002D Datasheet, PDF (13/38 Pages) SPANSION – 2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface

Preliminary Information
Instructions
All instructions, addresses, and data are shifted in and out of the device, starting
with the most significant bit. Serial Data Input (SI) is sampled on the first rising
edge of Serial Clock (SCK) after Chip Select (CS#) is driven Low. Then, the one-
byte instruction code must be shifted in to the device, most significant bit first,
on Serial Data Input (SI), each bit being latched on the rising edges of Serial
Clock (SCK). The instruction set is listed in Table 5.
Every instruction sequence starts with a one-byte instruction code. Depending on
the instruction, this might be followed by address bytes, or by data bytes, or by
both or none. Chip Select (CS#) must be driven High after the last bit of the in-
struction sequence has been shifted in.
In the case of a Read Data Bytes (READ), Read Status Register (RDSR), Fast Read
(FAST_READ) and Read ID (READ_ID), the shifted-in instruction sequence is fol-
lowed by a data-out sequence. Chip Select (CS#) can be driven High after any
bit of the data-out sequence is being shifted out to terminate the transaction.
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write
Status Register (WRSR), Write Enable (WREN), or Write Disable (WRDI) instruc-
tion, Chip Select (CS#) must be driven High exactly at a byte boundary,
otherwise the instruction is rejected, and is not executed. That is, Chip Select
(CS#) must driven High when the number of clock pulses after Chip Select (CS#)
being driven Low is an exact multiple of eight.
All attempts to access the memory array during a Write Status Register cycle,
Program cycle or Erase cycle are ignored, and the internal Write Status Register
cycle, Program cycle or Erase cycle continues unaffected
Instruction
WREN
WRDI
WRSR
RDSR
READ
FAST_READ
READ_ID
SE
BE
PP
SP
RES
Table 5. Instruction Set.
Description
One-Byte Instruction
Code
Address
Bytes
Status Register Operations
Write Enable
06H (0000 0110)
0
Write Disable
04H (0000 0100)
0
Write to Status Register
01H (0000 0001)
0
Read from Status Register
05H (0000 0101)
0
Read Operations
Read Data Bytes
03H (0000 0011)
3
Read Data Bytes at Higher Speed
0BH (0000 1011)
3
Read ID
ABH (1010 1011)
0
Erase Operations
Sector Erase
D8H (1101 1000)
3
Bulk (Chip) Erase
C7H (1100 0111)
0
Program Operations
Page Program
02H (0000 0010)
3
Dummy Power Savings Mode Operations
Software Protect
B9H (1011 1001)
0
Release from Software Protect
ABH (1010 1011)
0
Release from Software Protect and
Read Electronic Signature
ABH (1010 1011)
0
Dummy
Byte
Data Bytes
0
0
0
0
0
1
0
1 to Infinity
0
1 to Infinity
1
1 to Infinity
3
1 to Infinity
0
0
0
0
0
1 to 256
0
0
0
0
3
1 to Infinity
June 9, 2004 30167A+1
S25FL Family (Serial Peripheral Interface)
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