AM29DL32XG_06 Datasheet, PDF (12/58 Pages) SPANSION – 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

DATA SHEET
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Device Bus Operations
DQ15–DQ8
Operation
Read
Write
Standby
CE# OE# WE# RESET# WP#/ACC
L
L
H
H
L/H
L
H
L
H
(Note 3)
V_CC ±
0.3 V
X
X
V_CC ±
0.3 V
H
Addresses
(Note 2)
A_IN
A_IN
X
BYTE#
= V_IH
BYTE#
= V_IL
D_OUT
D_IN
DQ8–DQ14 =
High-Z, DQ15 = A-1
DQ7–
DQ0
D_OUT
D_IN
High-Z
High-Z
High-Z
Output Disable
L
HH
H
L/H
X
High-Z
High-Z
High-Z
Reset
X
X
X
L
L/H
X
High-Z
High-Z
High-Z
Sector Protect (Note 2)
L
H
L
V_ID
L/H
SA, A6 = L,
A1 = H, A0 = L
X
X
D_IN
Sector Unprotect (Note 2) L
H
L
V_ID
(Note 3)
SA, A6 = H,
A1 = H, A0 = L
X
X
D_IN
Temporary Sector
Unprotect
X
X
X
V_ID
(Note 3)
A_IN
D_IN
High-Z
D_IN
Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID = 8.5–12.5 V, V_HH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,
A_IN = Address In, D_IN = Data In, D_OUT = Data Out
Notes:
1. Addresses are A20:A0 in word mode (BYTE# = V_IH), A20:A-1 in byte mode (BYTE# = V_IL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
3. If WP#/ACC = V_IL, the two outermost boot sectors remain protected. If WP#/ACC = V_IH, the two outermost boot sector
protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block
Protection and Unprotection”. If WP#/ACC = V_HH, all sectors will be unprotected.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ0–DQ15 are active and controlled by
CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ7–DQ0 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V_IL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V_IH. The BYTE# pin determines
whether the device outputs array data in words or
bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
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Am29DL32xG
25686B10 December 4, 2006