S25FL032P0XBHIS20 Datasheet, PDF (11/69 Pages) SPANSION – 32-Mbit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus

Data Sheet
Figure 2.6 6x8 mm 24-ball BGA Package, 6x4 pin Configuration
A1
A2
A3
A4
NC
NC
NC
NC
B1
B2
B3
B4
NC
SCK
GND
VCC
C1
C2
C3
C4
NC
CS#
NC W#/ACC/IO2
D1
D2
D3
D4
NC SO/IO1 SI/IO0 HOLD#/IO3
E1
E2
E3
E4
NC
NC
NC
NC
F1
F2
F3
F4
NC
NC
NC
NC
3. Input/Output Descriptions
Signal
SO/IO1
SI/IO0
SCK
CS#
HOLD#/IO3
W#/ACC/IO2
V_CC
GND
I/O
I/O
I/O
Input
Input
I/O
I/O
Input
Input
Description
Serial Data Output: Transfers data serially out of the device on the falling edge of SCK.
Functions as an input pin in Dual and Quad I/O, and Quad Page Program modes.
Serial Data Input: Transfers data serially into the device. Device latches commands,
addresses, and program data on SI on the rising edge of SCK. Functions as an output pin in
Dual and Quad I/O mode.
Serial Clock: Provides serial interface timing. Latches commands, addresses, and data on SI on
rising edge of SCK. Triggers output on SO after the falling edge of SCK.
Chip Select: Places device in active power mode when driven low. Deselects device and places
SO at high impedance when high. After power-up, device requires a falling edge on CS# before
any command is written. Device is in standby mode when a program, erase, or Write Status
Register operation is not in progress.
Hold: Pauses any serial communication with the device without deselecting it. When driven low,
SO is at high impedance, and all input at SI and SCK are ignored. Requires that CS# also be
driven low. Functions as an output pin in Quad I/O mode.
Write Protect: Protects the memory area specified by Status Register bits BP2:BP0. When
driven low, prevents any program or erase command from altering the data in the protected
memory area. Functions as an output pin in Quad I/O mode.
Supply Voltage
Ground
January 29, 2013 S25FL032P_00_09
S25FL032P
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