S75WS256NXX Datasheet, PDF (109/216 Pages) SPANSION – Stacked Multi-Chip Product (MCP)

Data Sheet
Refer to the Synchronous/Burst Read section for RESET# parameters and to Figure 25.9 for the
timing diagram.
18.12 Output Disable Mode
When the OE# input is at V_IH, output from the device is disabled. The outputs are placed in the
high impedance state.
18.13
Hardware Data Protection
The following hardware data protection measures prevent accidental erasure or programming,
which might otherwise be caused by spurious system level signals during V_CC power-up and
power-down transitions, or from system noise.
18.13.1 Low V_CC Write Inhibit
When V_CC is less than V_LKO, the device does not accept any write cycles. This protects data during
V_CC power-up and power-down. The command register and all internal program/erase circuits are
disabled, and the device resets to reading array data. Subsequent writes are ignored until V_CC is
greater than V_LKO. The system must provide the proper signals to the control inputs to prevent
unintentional writes when V_CC is greater than V_LKO.
18.13.2 Write Pulse Glitch Protection
Noise pulses do not initiate a write cycle.
18.13.3 Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V_IL, CE# = V_IH or WE# = V_IH. To initiate
a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
February 17, 2005 S75WS-N-00_00_A0
S75WS256Nxx Based MCPs
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