AM75PDL191CHH_0402 Datasheet, PDF (107/136 Pages) SPANSION – 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory

ADVANCE INFORMATION
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
I_LI
Input Load Current
I_LIT
A9 Input Load Current
I_LO
Output Leakage Current
I_LR
Reset Leakage Current
I_CC1
V_CC Active Read Current
(Notes 1, 2)
V_IN = V_SS to V_CC,
V_CC = V_{CC max}
V_CC = V_{CC max}; A9 = 12.5 V
V_OUT = V_SS to V_CC,
V_CC = V_{CC max}
V_CC = V_{CC max}; RESET= 12.5 V
CE# = V_IL, OE# ₌ V_IH,
Byte Mode
5 MHz
1 MHz
CE# = V_IL, OE# = V_IH,
Word Mode
5 MHz
1 MHz
±1.0
µA
35
µA
±1.0
µA
35
µA
10
16
2
4
mA
10
16
2
4
I_CC2
V_CC Active Write Current (Notes 2, 3) CE# = V_IL, OE# = V_IH, WE# = V_IL
I_CC3
V_CC Standby Current (Note 2)
CE#, RESET# = V_CC ± 0.3 V
I_CC4
V_CC Reset Current (Note 2)
RESET# = V_SS ± 0.3 V
I_CC5
Automatic Sleep Mode (Notes 2, 4)
V_IH = V_CC ± 0.3 V;
V_IL = V_SS ± 0.3 V
I_CC6
V_CC Active Read-While-Program
Current (Notes 1, 2)
CE# = V_IL, OE# = V_IH
Word
15
30
mA
0.2
5
µA
0.2
5
µA
0.2
5
µA
21
45
mA
I_CC7
V_CC Active Read-While-Erase
Current (Notes 1, 2)
CE# = V_IL, OE# = V_IH Word
21
45
mA
V_CC Active
I_CC8
Program-While-Erase-Suspended CE# = V_IL, OE# = V_IH
Current (Notes 2, 5)
17
35
mA
V_IL
Input Low Voltage
V_IH
Input High Voltage
Voltage for WP#/ACC Sector
V_HH Protect/Unprotect and Program
Acceleration
V_CC = 3.0 V ± 10%
–0.5
0.7 x V_CC
8.5
0.8
V
V_CC + 0.3 V
9.5
V
V_ID
Voltage for Autoselect and Temporary
Sector Unprotect
V_CC = 3.0 V ± 10%
11.5
12.5
V
V_OL
Output Low Voltage
I_OL = 2.0 mA, V_CC = V_{CC min}
0.45
V
V_OH1
Output High Voltage
I_OH = –2.0 mA, V_CC = V_{CC min}
0.85 V_CC
V
V_OH2
I_OH = –100 µA, V_CC = V_{CC min}
V_CC–0.4
V_LKO Low V_CC Lock-Out Voltage (Note 5)
2.0
2.5
V
Notes:
1. The I_CC current listed is typically less than 2 mA/MHz, with OE# at V_IH.
2. Maximum I_CC specifications are tested with V_CC = V_CCmax.
3. I_CC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC + 30 ns. Typical sleep mode current is
200 nA.
5. Not 100% tested.
February 5, 2004
Am75PDL191CHH/Am75PDL193CHH
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