S70GL-P Datasheet, PDF (10/13 Pages) SPANSION – 2 Gigabit, 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology

Data Sheet
3. Memory Map
The S70GL02GP consist of uniform 64 Kword (128 Kb) sectors organized as shown in Table 3.1.
Uniform Sector
Size
64 Kword/128 Kb
Table 3.1 S70GL02GP Sector & Memory Address Map
Sector
Count
2048
Sector
Range
SA00
:
SA2047
Address Range (16-bit)
0000000h–000FFFFh
:
7FF0000H–7FFFFFFh
Notes
Sector Starting Address
Sector Ending Address
Note
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges
that are not explicitly listed (such as SA001-SA2046) have sector starting and ending addresses that form the same pattern as all other
sectors of that size. For example, all 128 Kb sectors have the pattern xxx0000h-xxxFFFFh.
4. Autoselect
Table 4.1 provides the device identification codes for the S70GL02GP. For more information on the
autoselect function, refer to the S29GL-P data sheet (publication number S29GL-P_00).
Table 4.1 Autoselect Addresses in System
Description
Manufacturer ID
Device ID, Word 1
Device ID, Word 2
Device ID, Word 3
Secure Device Verify
Sector Protect Verify
Address
(Base) + 00h
(Base) + 01h
(Base) + 0Eh
(Base) + 0Fh
(Base) + 03h
(SA) + 02h
Read Data (word/byte mode)
xx01h/1h
227Eh/7Eh
2248h/48h
2201h/01h
For S70GL02GPH: XX19h/19h = Not Factory Locked. XX99h/99h = Factory Locked.
For S70GL02GPL: XX09h/09h = Not Factory Locked. XX89h/89h = Factory Locked.
xx01h/01h = Locked, xx00h/00h = Unlocked
5. Erase And Programming Performance
Table 5.1 Erase And Programming Performance
Parameter
Typ
Max
(Note 1)
(Note 2)
Unit
Sector Erase Time
0.5
3.5
sec
Chip Erase Time
S70GL02GP
1024
4096
sec
Total Write Buffer Time, for 64 bytes
480
µs
Total Accelerated Write Buffer Programming Time, for 64
bytes
432
µs
Chip Program Time
S70GL02GP
1968
sec
Comments
Excludes 00h programming
prior to erasure (Note 3)
Excludes system level
overhead (Note 4)
Notes
1. Typical program and erase times assume the following conditions: 25°C, 3.6 V V_CC, 10,000 cycles, checkerboard pattern.
2. Under worst case conditions of -40°C, V_CC = 3.0 V, 100,000 cycles.
3. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
4. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.
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S70GL-P MirrorBit^® Flash
S70GL-P_00_03 February 23, 2010