XPP-XG-N1-CDFA Datasheet, PDF (4/13 Pages) –

XPP-XG-N1-CDFA
Data Output Differential Swing
Signal Detected Voltage_low
Signal Detected Voltage_high
Signal Detected Assert Time
Signal Detected Deassert Time
Data Output Rise Time
Data Output Fall Time
Reset Signal Width
Guard Time
Receiver Settling Time
RSSI Trigger Delay
RSSI Sampling Time
Internal I²C Delay
Receiver
VOUT
VSD, L
VSD, H
TSDA
TSDD
Tr
Tf
T_RW
Tg
T_settling
T_trigger
T__sampling
TI2C
700
0
2.4
25.6
25.6
25
500
950
mVP-P
3
0.8
V
4
VCC3
V
100
ns
5
12.8
ns
140
ps
5
140
ps
ns
ns
140
ns
6
ns
7
ns
8
500
us
Notes:
1. Compatible with CML input, AC coupled internally. (See Recommended Interface Circuit)
2. TX Disable (See Pin Function Definitions).
3. CML output, DC coupled internally, guaranteed in the full range of input optical power (-7dBm to
-27.5dBm) (See Recommended Interface Circuit).
4. SD (See Pin Function Definitions).
5. Amount time is from the reset signal is coming to the bust signal reaches a appropriate value
6. Test at 0101 pattern@2.488Gbps, 20% to 80% full swing
7. Falling edge of reset signal should be after the rising edge of the first preamble bit, test@1010 pattern
8. RSSI Input signal rising edge will trigger RSSI sampling, and falling edge will trigger internal digital
RSSI information written to I2C. It is recommended that host shall not trigger RSSI input again until
RSSI data is valid in I2C from previous RSSI trigger.
4
DS- 6237 Rev 04 2012-03-05