C-127-2500-FDFB-SLC2 Datasheet, PDF (4/10 Pages) Source Photonics, Inc. – 2.5 Gbps Single Mode SFF LC Transceiver

2.5 Gbps Single Mode SFF LC Transceiver
C-1XX-2500(C)-FDFB-SLCX
Recommended Circuit Schematic
Inputs to the C-1XX-2500(C)-FDFB-SLCX series transmitters are AC coupled and internally terminated through 50 ohms to AC ground.
These transceivers can operate with LVPECL or CML logic levels. The input signal must have at least a 200 mV peak to (single ended) signal
swing. Output from the receiver section of the module is also AC coupled and is expected to drive into 50 ohm load. Different termination
strategies may be required depending on the particular Serializer / Deserializer chip set used.
The C-1XX-2500(C)-FDFB-SLCX series product family are designed with AC coupled data inputs and outputs to provide the following
advantages:
■ Close positioning of SERDES with respect to transceiver; allows for shorter line lengths and at gigabit speeds reduces EMI.
■ Minimum number of external components.
■ Internal termination reduces the potential for unterminated stubs which would otherwise increase jitter and reduce transmission
margin.
Figure 1 & Figure 2 illustrates the recommended transmit and receive data line trminations for SERDES with CML and LVPECL Inputs / Outputs
respectively.
TRANSMITTER
DRIVER
LASER
BIAS
TZ
PIN
AMP
POST
AMP
RECEIVER
TX_DIS ⁸
TX_GND ⁷
TX_D ₉
TX_D _�0
Vcc_TX 6
Vcc_RX ²
3
SD
RX_D ₄
RX_D ₅
RX_GND ^�
TTL logic level
Z=50�
Z=50�
See
Fig. 4A
See
Fig. 3
Z=50�
Z=50�
Note �
TD +
TD -
Serializer / De-Serializer
with CML lnputs/Outputs
RD -
RD +
Figure 1.Recommended TRANSMIT and RECEIVE Data Terminations for SERDES with CML I/Os.
Note 1. Consult SERDES manufacturer’s data sheet and application data for appropriate receiver input biasing network.
Some deserializer inputs are internally terminated and may not need external termination resistors.
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4
LUMNDS851-Jul2005
rev. A.0