CXD2548R Datasheet, PDF (98/113 Pages) Sony Corporation – CD Digital Signal Processor with Built-in Digital Servo and DAC

CXD2548R
SDF2, SDF1: DFCT slice level
Default value: 10 (179mV)
RFDC input conversion
SDF2
0
0
1
1
SDF1
0
1
0
1
Slice level
89mV
134
179
224
MAX2, MAX1: DFCT maximum time
Default value: 00 (no timer limit)
MAX2
0
0
1
1
MAX1
0
1
0
1
DFCT maximum time
No timer limit
2.00ms
2.36
2.72
BTF:
Bottom hold double-speed count-up mode for MIRR signal generation
On/off (default: off)
On when set to 1.
D2V2, D2V1: Peak hold 2 for DFCT signal generation
Count-down speed setting
Default value: 01 (0.492V/ms, 44.1kHz)
[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the
operating frequency of the internal counter.
D2V2
0
0
1
1
D2V1
0
1
0
1
Count-down speed
[V/ms]
0.246
0.492
0.984
1.969
[kHz]
22.05
44.1
88.2
176.4
D1V2, D1V1: Peak hold 1 for DFCT signal generation
Count-down speed setting
Default value: 01 (3.938V/ms, 352.8kHz)
[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the
operating frequency of the internal counter.
D1V2
0
0
1
1
D1V1
0
1
0
1
Count-down speed
[V/ms]
[kHz]
1.969
3.938
7.875
15.75
176.4
352.8
705.6
1411.2
RINT:
This initializes the initial-stage registers of the circuits which generate MIRR, DFCT and FOK.
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