CXD3021R Datasheet, PDF (71/161 Pages) Sony Corporation – CD Digital Signal Processor with Built-in Digital Servo and DAC

Timing Chart 1-19
CAV-W mode EPWM = 1, DCLV PWM MD = LPWR = 0
H
PWMI
L
H
MDP
L
Acceleration
Timing Chart 1-20
CAV-W mode EPWM = 1, DCLV PWM MD = 0, LPWR = 1
H
PWMI
L
H
Z
MDP
Acceleration
CXD3021R
Deceleration
The BRAKE pulse is masked when LPWR = 1.
Note) CLV-W and CAV-W modes support control only by the ternary output of the MDP pin.
Therefore, set DCLV PWM MD to 0 in CLV-W and CAV-W modes.
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