CXD3220R Datasheet, PDF (7/65 Pages) Sony Corporation – IEEE1394 Link/Transaction Layer Controller LSI for SBP-2

Pin
No.
Symbol
I/O
Description
68 SD5
I/O Transport data I/F data bus bit 5
69 SD6
I/O Transport data I/F data bus bit 6
70 SD7
I/O Transport data I/F data bus bit 7
71 SD8
I/O Transport data I/F data bus bit 8
72 SD9
I/O Transport data I/F data bus bit 9
73 SD10
I/O Transport data I/F data bus bit 10
74 SD11
I/O Transport data I/F data bus bit 11
75 SD12
I/O Transport data I/F data bus bit 12
76 VDD
— Power supply
77 VSS
— GND
78 SD13
I/O Transport data I/F data bus bit 13
79 SD14
I/O Transport data I/F data bus bit 14
80 SD15
I/O Transport data I/F data bus bit 15
81 SDRQ
O Transport data I/F data request signal
82 XSAC
83 TEST21
84 TEST22
85 TEST23
86 TEST24
I Transport data I/F acknowledge signal
— Test pin^∗1
— Test pin^∗1
— Test pin^∗1
— Test pin^∗1
87 X8/16
I
CPU I/F I/O data bus select signal
0: 8 bits; 1:16 bits
88 VSS
— GND
89 XWAIT
O
CPU I/F wait signal
active when XCS = 0,
high impedance when XCS = 1
90 XINT
O
CPU I/F interrupt signal
0: Active; 1: Non-active
91 XCS
I
CPU I/F chip select signal
0: Active; 1: Non-active
92 ADDRESS0 I CPU I/F address bus bit 0
93 ADDRESS1 I CPU I/F address bus bit 1
94 ADDRESS2 I CPU I/F address bus bit 2
95 ADDRESS3 I CPU I/F address bus bit 3
96 ADDRESS4 I CPU I/F address bus bit 4
97 ADDRESS5 I CPU I/F address bus bit 5
98 ADDRESS6 I CPU I/F address bus bit 6
99 DATA0
I/O CPU I/F I/O data bit 0
100 DATA1
I/O CPU I/F I/O data bit 1
∗1 _{The test pins should be used open.}
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CXD3220R