CXD2587Q Datasheet, PDF (66/106 Pages) Sony Corporation – CD Digital Signal Processor with Built-in Digital Servo and DAC

CXD2587Q
§4-2. Digital Servo Block Master Clock (MCK)
The clock with the 2/3 frequency of the crystal is supplied to the digital servo block.
The XT4D and XT2D command can be set with D13 and D12 of $3F, and the XT1D command can be set with
D1 of $3E. (Default = 0)
The digital servo block is designed with an MCK frequency of 5.6448MHz (128Fs) as typical.
Mode
1
2
3
4
5
6
7
XTLI
384Fs
384Fs
384Fs
768Fs
768Fs
768Fs
768Fs
Input to servo
256Fs
256Fs
256Fs
512Fs
512Fs
512Fs
512Fs
XTSL
∗
∗
0
∗
∗
∗
1
XT4D
∗
∗
0
∗
∗
1
0
XT2D
∗
1
0
∗
1
0
0
Table 4-1.
XT1D
1
0
0
1
0
0
0
Frequency division ratio MCK
1
256Fs
1/2
128Fs
1/2
128Fs
1
512Fs
1/2
256Fs
1/4
128Fs
1/4
128Fs
Fs = 44.1kHz, ∗: Don’t care
§4-3. AVRG (Average) Measurement and Compensation
The CXD2587Q has a circuit that measures the averages of RFDC, VC, FE and TE and a circuit that
compensates these signals to control the servo effectively.
AVRG measurement and compensation is necessary to initialize the CXD2587Q, and is able to cancel the
offset.
The level applied to the VC, FE, RFDC and TE pins can be measured by setting D15 (VCLM), D13 (FLM), D11
(RFLM) and D4 (TCLM) of $38 respectively to 1.
AVRG measurement takes the level applied to each analog input pin as the average of 256 samples, and then
loads each value into the AVRG register.
AVRG measurement requires approximately 2.9ms to 5.8ms (when MCK = 128Fs) after the command is
received.
During AVRG measurement, if the upper 8 bits of the command register are 38 (Hex), the completion of AVRG
measurement operation can be confirmed through the SENS pin. (See Timing Chart 4-2.)
XLAT
SENS
(= XAVEBSY)
2.9 to 5.8ms
Max. 1µs
Timing Chart 4-2.
AVRG measurement completed
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