CXA3516R Datasheet, PDF (64/110 Pages) Sony Corporation – 3-channel 8-bit 165MSPS A/D Converter Amplifier PLL

CXA3516R
CLK Jitter Evaluation Method
The generated CLK is obtained by inputting Hsync to the CXA3516R. Apply this CLK to a digital oscilloscope
and observe the CLK waveform using Hsync as the trigger.
Pulse
Hsync signal
generator
Clock
CXA3516R
trigger
Digital
oscilloscope
ch1
H Back
sync porch
Active
video
Front
porch
Computer signal
Hsync signal
15 to 25% of Tsync
Tsync = 1/fsync
Clock
Trigger
Enlarge ^Enlarge
Enlarge
Enlarge
Clock
Tj p-p
The CLK jitter is measured at peak to peak in the long-term write mode of the digital oscilloscope as shown in
the figure. The CLK jitter size varies according to the difference in the relative position with respect to Hsync.
Therefore, when the observation point is changed, the CLK jitter at that point is observed.
The figure below shows a typical example of the CLK jitter for the CXA3516R.
The CLK jitter increases slightly at the rising edge of Hsync (in the case of positive polarity), and then settles
down thereafter. However, this is not a problem as the active pixels start after about 20% of the H cycle has
passed from the rising edge of Hsync.
0
1/4 · Tsync
2/4 · Tsync
3/4 · Tsync
Tsync
Observation points
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