CXD3526GG Datasheet, PDF (46/88 Pages) Sony Corporation – Digital Signal Driver/Timing Generator

CXD3526GG
If correction is to be performed in the gradual direction as well, the RAM address is found based on the
relationship between the coordinates (m, n) of the correction points and the number of gradual correction
points using the formula below:
RAM address = (m – 1) + (n – 1) × (number of horizontal correction points)
+ (number of horizontal correction points) × (number of vertical correction points)
× (number of gradual correction points – 1)
If the number of gradual correction points is eight, it is necessary to set correction data into RAM from Address
0 to Address 503 as calculated below:
(9 – 1) + (7 – 1) × 9 + 9 × 7 × 7 = 503
Correction data in the gradual direction for the screen 2 and subsequent planes is set in order from Address 63.
This IC supports top/bottom and/or right/left inversion of the LCD panel by controlling the direction in which
correction data that has been set into RAM is read. Up/down and/or right/left inversion are set from DWN and
RGT of the TG block.
CSC_DWN and CSC_R (G, B)_RGT control the link with the TG block settings. It is therefore unnecessary to
reset correction data. The table below gives an example of setting correction points.
Signal specification
XGA (1024 × 768)
SVGA (800 × 600)
Correction gap
H
V
64
64
64
64
50
50
64
64
64
64
Number of correction points
H
V
G
Total
17
13
8
1768
16
12
8
1536
17
13
8
1768
14
11
8
1232
13
10
8
1040
Example of Setting Correction Points
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