CXD1198AQ Datasheet, PDF (45/51 Pages) Sony Corporation – CD-ROM Subcode Decoder

CXD1198AQ
♦ When the host DMA enable bit is set to “0”
Data transfer is stopped when the host DMA enable bit is set to “0” during actual transfer. Then
the transfer of data between this IC and the host or buffer memory may be suspended so that the
values of the Host Address Counter and Host Transfer Counter after suspension cannot be
guaranteed.
In this case, the host DMA complete status does not set on.
(4) Procedure for controlling IC from CPU
Described below is the procedure for controlling this IC when DMA transfer of the host DMA channel is to
be executed.
♦ Write the number of bytes transferred into the Host DMA Transfer Counter.
♦ Write the head address of the buffer memory, to which the data is transferred by DMA, into the
Host DMA Address Counter.
♦ Write “1” into Bit 0 (host DMA enable) of DMA Control Register-2 and “0” or “1” into Bit 1 (host
DMA source), depending on the transfer direction. (When these are written, the DMA cycle
execution commences.)
♦ When the DMA transfer of the number of bytes written into the Host DMA Transfer Counter is
completed, Bit 3 (host DMA complete) of the Interrupt Status Register is set to to “1”. Also, the
Host DMA Transfer Register is zero, and the Host DMA Address Counter holds the value of the
address following the buffer memory address which was last transferred by DMA.
4-3. When connecting this IC with the SCSI control LSI
When connecting this IC to the SCSI control LSI, input a high logic level to the HMDS pin. Fig. 4-4 shows
an example of the connections.
(1) Data transfer between SCSI control LSI and buffer memory
Data is transferred between the SCSI control LSI and this IC by means of handshaking using the
HDRQ/XSAC and XHAC/SDRQ pins.
The XHAC/SDRQ pin outputs the SDRQ signal requesting data transfer from the SCSI control LSI to this
IC, and the HDRQ/XSAC pin becomes the corresponding acknowledge signal XSAC.
♦ Data transfer from SCSI control LSI to buffer memory (host DMA source bit = “1”)
When the host DMA enable bit is “1”, and the SDRQ signal is input, this IC outputs a low-level
signal from the XSAC pin provided that FIFO is not full. The data is retrieved in this IC at the
XHWR pin rising. The data retrieved is written in sequence into the addresses of the buffer
memory selected by the host address counter.
♦ Data transfer from buffer memory to SCSI control LSI (host DMA source bit = “0”)
When the host DMA enable bit is “1”, the data in the address of the buffer memory selected by the
Host Address Counter is retrieved in this IC. When, with the buffer memory data retrieved, the
SDRQ signal X is input, this IC outputs a low-level signal from the XSAC pin and, while this pin is
low, the IC outputs the data retrieved from the buffer memory to host bus HDB0 to 7.
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