ICX424AQ Datasheet, PDF (4/27 Pages) Sony Corporation – Diagonal 6mm Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras

ICX424AQ
Bias Conditions
Item
Symbol Min. Typ. Max. Unit Remarks
Supply voltage
VDD
14.55 15.0 15.45 V
Protective transistor bias
VL
∗1
Substrate clock
φSUB
∗2
Reset gate clock
φRG
∗3
∗1 _{VL setting is the VVL voltage of the vertical transfer clock waveform, or the same voltage as the VL power}
supply for the V driver should be used.
∗2 _{Set SUBCIR pin to open when applying a DC bias to the substrate clock pin.}
∗3 _{Do not apply a DC bias to the reset gate clock pins, because a DC bias is generated within the CCD.}
DC Characteristics
Item
Supply current
Symbol Min. Typ. Max. Unit Remarks
IDD
7
9
mA
Clock Voltage Conditions
Item
Symbol
Min.
Readout clock voltage
VVT
14.55
VVH02
–0.05
VVH1, VVH2, VVH3 –0.2
VVL1, VVL2, VVL3 –7.8
Vertical transfer clock
voltage
VVL1, VVL2, VVL3
Vφ1, Vφ2, Vφ3
| VVL1 – VVL3 |
VVHH
VVHL
VVLH
VVLL
VφH
Horizontal transfer
clock voltage
VHL
VCR
Reset gate clock
voltage
VφRG
VRGLH – VRGLL
VRGL – VRGLm
Substrate clock voltage VφSUB
–8.0
6.8
4.75
–0.05
0.8
4.5
21.5
Typ.
15.0
0
0
–7.5
–7.5
7.5
5.0
0
2.5
5.0
22.5
Max.
Unit
Waveform
Diagram
Remarks
15.45 V
1
0.05 V
2
VVH = VVH02
0.05 V
2
–7.2 V
2
VVL = VVL1 (VVL3)/2
(During 24.54MHz)
–7.0 V
2
VVL = VVL1 (VVL3)/2
(During 12.27MHz)
8.05 V
2
0.1 V
2
1.0 V
2
High-level coupling
2.3 V
2
High-level coupling
1.0 V
2
Low-level coupling
1.0 V
2
Low-level coupling
5.25 V
3
0.05 V
3
V
3
Cross-point voltage
5.5 V
4
0.8 V
4
Low-level coupling
0.5 V
4
Low-level coupling
23.5 V
5
–4–