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ICX412AQF Datasheet, PDF (4/30 Pages) Sony Corporation – Diagonal 8.933mm (Type 1/1.8) Frame Readout CCD Image Sensor with a Square Pixel for Color Cameras | |||
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ICX412AQF
Bias Conditions
Item
Symbol
Min.
Typ.
Max.
Unit Remarks
Supply voltage
VDD
14.55
15.0
15.45
V
Protective transistor bias
VL
â1
Substrate clock
ÏSUB
â2
Reset gate clock
ÏRG
â2
â1 VL setting is the VVL voltage of the vertical clock waveform, or the same voltage as the VL power supply for
the V driver should be used.
â2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
Item
Supply current
Symbol
Min.
Typ.
Max.
Unit Remarks
IDD
5.5
7.5
9.5
mA
Clock Voltage Conditions
Item
Symbol
Min.
Readout clock voltage VVT
14.55
VVH1, VVH2
â0.05
VVH3, VVH4
â0.2
VVL1, VVL2,
VVL3, VVL4
â8.0
Vertical transfer clock
voltage
VÏV
VVH3 â VVH
VVH4 â VVH
6.8
â0.25
â0.25
VVHH
VVHL
VVLH
VVLL
VÏH
Horizontal transfer
clock voltage
VHL
VCR
4.0
â0.05
0.8
Reset gate clock
voltage
VÏRG
3.0
VRGLH â VRGLL
VRGL â VRGLm
Substrate clock voltage VÏSUB
21.5
Typ.
15.0
0
0
â7.5
7.5
5.0
0
2.5
3.3
22.5
Max.
Unit
Waveform
Diagram
Remarks
15.45 V
1
0.05 V
2
VVH = (VVH1 + VVH2)/2
0.05 V
2
â7.0 V
2
VVL = (VVL3 + VVL4)/2
8.05 V
0.1 V
0.1 V
0.8 V
0.9 V
0.9 V
0.8 V
5.25 V
0.05 V
V
5.25 V
0.4 V
0.5 V
23.5 V
2
VÏV = VVHn â VVLn (n = 1 to 4)
2
2
2 High-level coupling
2 High-level coupling
2 Low-level coupling
2 Low-level coupling
3
3
3 Cross-point voltage
4
4 Low-level coupling
4 Low-level coupling
5
â4â
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