ICX406AQF Datasheet, PDF (4/33 Pages) Sony Corporation – Diagonal 8.98mm (Type 1/1.8) Frame Readout CCD Image Sensor with a Square Pixel for Color Cameras

ICX406AQF
Bias Conditions
Item
Supply voltage
Protective transistor bias
Substrate clock
Reset gate clock
Symbol
VDD
VL
φSUB
φRG
Min.
14.55
Typ.
15.0
∗1
∗2
∗2
Max.
15.45
Unit Remarks
V
∗1 _{VL setting is the VVL voltage of the vertical clock waveform, or the same voltage as the VL power supply}
for the V driver should be used.
∗2 _{Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated}
within the CCD.
DC Characteristics
Item
Supply current
Symbol
Min.
Typ.
Max.
Unit Remarks
IDD
3.0
7.0
10.0
mA
Clock Voltage Conditions
Item
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock voltage
Symbol
Min.
VVT
14.55
VVH1, VVH2
–0.05
VVH3, VVH4
–0.2
VVL1, VVL2,
VVL3, VVL4
–8.0
VφV
6.8
VVH3 – VVH
–0.25
VVH4 – VVH
–0.25
VVHH
VVHL
VVLH
VVLL
VφH
4.75
VHL
–0.05
VCR
0.8
VφRG
3.0
VRGLH – VRGLL
VRGL – VRGLm
VφSUB
21.5
Typ.
15.0
0
0
–7.5
7.5
5.0
0
2.5
3.3
22.5
Max.
Unit
Waveform
Diagram
15.45 V
1
0.05 V
2
0.05 V
2
–7.0 V
2
8.05 V
2
0.1 V
2
0.1 V
2
0.9 V
2
0.9 V
2
0.9 V
2
0.7 V
2
5.25 V
3
0.05 V
3
V
3
5.25 V
4
0.4 V
4
0.5 V
4
23.5 V
5
Remarks
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Cross-point voltage
Low-level coupling
Low-level coupling
–4–