ICX274AQF Datasheet, PDF (4/72 Pages) Sony Corporation – Diagonal 8.923mm (Type 1/1.8) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras

ICX274AQF
Bias Conditions
Item
Symbol
Min.
Typ.
Max. Unit Remarks
Supply voltage
Protective transistor bias
Substrate voltage ^{No line addition∗1}
adjustment range _{2-line addition}∗2
VDD
VL
VSUB
VSUB2
14.55
15.0
15.45
∗3
Internally generated value
8.8
14.4
V
∗4
V
Substrate voltage adjustment accuracy
Reset gate clock
∆VSUB
φRG
Indicated
voltage – 0.2
Indicated
voltage
∗5
Indicated
voltage + 0.2
V
V
∗1 _{Progressive scan mode, 2/8-line readout mode, 2/4-line readout mode, center scan modes (1) and (3),}
and AF modes (1) and (2)
∗2 _{2-line addition mode and center scan mode (2)}
∗3 _{VL setting is the VVL voltage of the vertical clock waveform, or the same voltage as the VL power supply}
for the V driver should be used.
∗4 _{Substrate voltage (VSUB2) setting value indication}
The substrate voltage (VSUB) for modes without line addition is generated internally.
The substrate voltage setting value for use with vertical 2-line addition is indicated by a code on the
bottom surface of the image sensor. Adjust the substrate voltage to the indicated voltage.
VSUB2 code – 1-digit indication
↑
VSUB2 code
The code and the actual value correspond as follows.
VSUB2 code 1 2 3 4 6 7 8 9 A C d E f G h
Actual value 8.8 9.0 9.2 9.4 9.6 9.8 10.0 10.2 10.4 10.6 10.8 11.0 11.2 11.4 11.6
VSUB2 code J K L m N P R S U V W X Y Z
Actual value 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 13.4 13.6 13.8 14.0 14.2 14.4
[Example] "h" indicates a VSUB2 setting of 11.6V.
∗5 _{Do not apply a DC bias to the reset gate clock pin, because a DC bias is generated within the CCD.}
DC characteristics
Item
Supply current
Symbol
Min.
IDD
7.0
Typ.
10.0
Max.
13.0
Unit Remarks
mA
–4–