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ICX252AK Datasheet, PDF (4/30 Pages) Sony Corporation – Diagonal 8.933mm (Type 1/1.8) Frame Readout CCD Image Sensor with Square Pixel for Color Cameras | |||
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ICX252AK
Bias Conditions
Item
Symbol Min. Typ. Max. Unit Remarks
Supply voltage
VDD
14.55 15.0 15.45 V
Protective transistor bias
VL
â1
Substrate clock
ÏSUB
â2
Reset gate clock
ÏRG
â2
â1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same voltage as the VL power
supply for the V driver should be used.
â2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
Item
Supply current
Symbol Min. Typ. Max. Unit Remarks
IDD
2.0
4.5
7.0 mA
Clock Voltage Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks
Readout clock voltage VVT
14.55 15.0 15.45 V
1
VVH1, VVH2
â0.05 0 0.05 V
2
VVH = (VVH1 + VVH2)/2
VVH3, VVH4
â0.2 0 0.05 V
2
VVL1, VVL2,
VVL3, VVL4
â8.0 â7.5 â7.0 V
2
VVL = (VVL3 + VVL4)/2
Vertical transfer clock
voltage
VÏV
VVH3 â VVH
VVH4 â VVH
6.8 7.5 8.05 V
â0.25
0.1 V
â0.25
0.1 V
2
VÏV = VVHn â VVLn (n = 1 to 4)
2
2
VVHH
0.6 V
2
High-level coupling
VVHL
0.9 V
2
High-level coupling
VVLH
0.9 V
2
Low-level coupling
VVLL
0.5 V
2
Low-level coupling
VÏH
Horizontal transfer
clock voltage
VHL
VCR
4.75 5.0 5.25 V
â0.05 0 0.05 V
0.8 2.5
V
3
3
3
Cross-point voltage
Reset gate clock
voltage
VÏRG
3.0 3.3 5.25 V
VRGLH â VRGLL
0.4 V
VRGL â VRGLm
0.5 V
4
4
Low-level coupling
4
Low-level coupling
Substrate clock voltage VÏSUB
21.5 22.5 23.5 V
5
â4â
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